Memory hub providing cache coherency protocol system method for multiple processor sockets comprising multiple XPUs

A method comprising:

• a memory hub providing multiple processor sockets with approximately uniform access times to multiple memory devices independent from increasing a number of memory channels at a processor socket to the multiple memory devices, wherein:
• the memory hub comprises a home agent to maintain cache coherency among the multiple processor sockets,
• the cache coherency among the multiple processor sockets comprises access a copy of modified content of a cache line,
• the multiple processor sockets comprise multiple XPUs, and
• the multiple XPUs comprise multiple cores.

At least one non-transitory computer-readable medium, comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:

• cause multiple processor sockets to send memory access requests to a memory hub, wherein
• the memory hub provides the multiple processor sockets with approximately uniform access times to one or more memory devices,
• the memory hub comprises a home agent to maintain cache coherency among the multiple processor sockets,
• the cache coherency among the multiple processor sockets comprises access a copy of modified content of a cache line,
• the multiple processor sockets comprise multiple XPUs, and
• the multiple XPUs comprise multiple cores.

A system comprising:

• a first central processing unit (CPU) socket;
• a second CPU socket;
• a first memory hub comprising a first home agent;
• and
• a second memory hub comprising a second home agent, wherein:
• the first home agent of the first memory hub is to maintain cache coherency among the first and second CPU sockets,
• the cache coherency among the first and second CPU sockets comprises access a copy of modified content of a cache line,
• the first and second CPU sockets comprise at least one core,
• the first CPU socket is to issue memory access request to the first memory hub to access a memory device connected to the first memory hub,
• the first CPU socket is to issue memory access request to the second memory hub to access a second memory device connected to the second memory hub,
• the second CPU socket is to issue memory access request to the first memory hub to access the memory device connected to the first memory hub, and
• the second CPU socket is to issue memory access request to the second memory hub to access the second memory device connected to the second memory hub.