Methods and devices for controlling memory handling
AssigneeTelefonaktiebolaget LM Ericsson (publ)
InventorsAmir Roozbeh, Alireza Farshin, Dejan Kostic, Gerald Q Maguire, Jr.
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AssigneeTelefonaktiebolaget LM Ericsson (publ)
InventorsAmir Roozbeh, Alireza Farshin, Dejan Kostic, Gerald Q Maguire, Jr.
Estimating the term…
A method and device for controlling memory handling in a processing system comprising a cache shared between a plurality of processing units, wherein the cache comprises a plurality of cache portions. The method comprises obtaining first information pertaining to an allocation of a first memory portion of a memory to a first application, an allocation of a first processing unit of the plurality of processing units to the first application, and an association between a first cache portion of the plurality of cache portions and the first processing unit. The method further comprises reconfiguring a mapping configuration based on the obtained first information, and controlling a providing of first data associated with the first application to the first cache portion from the first memory portion using the reconfigured mapping configuration.
A method for controlling memory handling in a processing system comprising a cache and a plurality of processing units, wherein the cache is a last level cache shared among the plurality of processing units and wherein the last level cache has a plurality of cache portions allocated respectively to corresponding processing units of the plurality of processing units, in which a first cache portion of the plurality of cache portions is allocated to a first processing unit of the plurality of processing units, the method comprising:
A device for controlling memory handling in a processing system comprising a cache and a plurality of processing units, wherein the cache is a last level cache shared among the plurality of processing units and wherein the last level cache has a plurality of cache portions allocated respectively to corresponding processing units of the plurality of processing units, in which a first cache portion of the plurality of cache portions is allocated to a first processing unit of the plurality of processing units, the device configured to:
A non-transitory computer-readable storage medium comprising instructions which, when executed by at least one processor, cause the at least one processor to perform operations for controlling memory handling in a processing system comprising a cache and a plurality of processing units, wherein the cache is a last level cache shared among the plurality of processing units and wherein the last level cache has a plurality of cache portions allocated respectively to corresponding processing units of the plurality of processing units, in which a first cache portion of the plurality of cache portions is allocated to a first processing unit of the plurality of processing units, comprising:
Dependencies are inferred from the claim text.