Prefetch circuit for cache memory
AssigneeCadence Design Systems, Inc.
InventorAvishai Tvila
Life of this patent
Estimating the term…
Abstract
A prefetch circuit coupled to a cache memory circuit includes a storage circuit that stores multiple virtual-to-physical address map entries. In response to receiving an indication of a miss for an access request to the cache memory circuit, the prefetch circuit generates a prefetch address and compares it to a demand address included in the access request. In response to determining that the demand address and the prefetch address are in different memory pages, the prefetch circuit generates a prefetch request using physical page information retrieved from the storage circuit.
Claims11
An apparatus, comprising:
- a cache memory circuit configured to:
- store a plurality of lines associated with a corresponding plurality of addresses;
- and
- receive an access request that includes a demand address corresponding to data included in a particular memory page identified by a particular physical page number;
- and
- a prefetch circuit including a storage circuit configured to store a plurality of virtual-to-physical map entries, wherein the prefetch circuit is configured to:
- generate a prefetch address using the demand address and a page offset;
- in response to receiving an indication from the cache memory circuit that a particular line associated with the demand address is not stored in the cache memory circuit, generate a prefetch request using a different physical page number in response to a determination that the prefetch address is not included in the particular memory page;
- and
- wherein the prefetch circuit is further configured to:
- perform a training operation using a plurality of virtual addresses corresponding to physical addresses included in a plurality of accesses to the cache memory circuit;
- in response to a determination that a number of times a memory page boundary was crossed during the training operation exceeds a threshold value, activate a cross page mode that tracks a number of page boundary crossings during the training operation;
- and
- update the page offset using a result of the training operation.
A method, comprising:
- generating, by a prefetch circuit, a first prefetch address using a first offset and a first demand address included in an access request to a cache memory circuit, wherein the first demand address is included in a first memory page identified by a first physical page number;
- and
- in response to receiving, by the prefetch circuit, a first indication from the cache memory circuit that first data associated with the first demand address is not stored in the cache memory circuit:
- generating a page offset using the demand address and the first offset;
- generating a prefetch request using the page offset and a different physical page number in response to determining that the prefetch address is not included in the first memory page;
- performing a training operation using a plurality of virtual addresses corresponding to physical addresses included in a plurality of accesses to the cache memory circuit;
- in response to determining that a number of times a memory page boundary was crossed during the training operation exceeds a threshold value, activating, by the prefetch circuit, a cross page mode that tracks a number of page boundary crossings during the training operation;
- and
- updating the page offset using a result of the training operation.
Dependencies are inferred from the claim text.