Dynamic inclusive last level cache
AssigneeIntel Corporation
InventorsAyan Mandal, Leon Polishuk, Oz Shitrit, Joseph Nuzman
Life of this patent
Estimating the term…
Abstract
An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.
Claims14
An integrated circuit, comprising:
- a core;
- and
- a cache controller coupled to the core, the cache controller including circuitry to:
- increment a counter value when a hit in a next level cache corresponds to an eviction from a core cache;
- perform an evaluation to test for a condition wherein:
- a current data hit corresponds to another eviction from the core cache, the current data hit comprising data from a working set;
- and
- the counter value is greater than a threshold;
- wherein, where the evaluation indicates a presence of the condition, the circuitry is further to:
- identify the data from the working set for dynamic inclusion in the next level cache;
- send a shared copy of the identified data to a requesting core of one or more processor cores;
- maintain a copy of the identified data in the next level cache;
- and
- set a snoop filter to indicate that the requesting core is valid for the current data hit.
A method of controlling a cache, the method comprising:
- incrementing a counter value when a hit in a next level cache corresponds to an eviction from a core cache;
- performing an evaluation to test for a condition wherein:
- a current data hit corresponds to another eviction from the core cache, the current data hit comprising data from a working set;
- and
- the counter value is greater than a threshold;
- and
- where the evaluation indicates a presence of the condition:
- identifying the data from the working set for dynamic inclusion in the next level cache;
- sending a shared copy of the identified data to a requesting core of one or more processor cores;
- maintaining a copy of the identified data in the next level cache;
- and
- setting a snoop filter to indicate that the requesting core is valid for the current data hit.
An apparatus, comprising:
- one or more processor cores;
- a core cache co-located with and communicatively coupled to the one or more processor cores;
- a next level cache co-located with and communicatively coupled to the core cache and the one or more processor cores;
- and
- a cache controller co-located with and communicatively coupled to the core cache, the next level cache, and the one or more processor cores, the cache controller including circuitry to:
- increment a counter value when a hit in a next level cache corresponds to an eviction from a core cache;
- perform an evaluation to test for a condition wherein:
- a current data hit corresponds to another eviction from the core cache, the current data hit comprising data from a working set;
- and
- the counter value is greater than a threshold;
- wherein, where the evaluation indicates a presence of the condition, the circuitry is further to:
- identify the data from the working set for dynamic inclusion in the next level cache,
- send a shared copy of the identified data to a requesting core of the one or more processor cores;
- maintain a copy of the identified data in the next level cache;
- and
- set a snoop filter to indicate that the requesting core is valid for the current data hit.
Dependencies are inferred from the claim text.