Synchronized request handling at a memory device
AssigneeMicron Technology, Inc.
InventorsTony M. Brewer, Dean E. Walker
Life of this patent
Estimating the term…
Abstract
System and techniques for synchronized request handling at a memory device are described herein. A request is received at the memory device. Here, the request indicates a memory address corresponding to a set of cache lines and a single cache line in the set of cache lines. The memory device maintains a deferred list for the set of cache lines and a set of lists with each member of the set of lists corresponding to one cache line in the set of cache lines. The memory device tests the deferred list to determine that the deferred list is not empty and places the request in the deferred list.
Claims24
An apparatus comprising:
- a set of cache lines;
- an interface to receive that indicates a memory address corresponding to the set of cache lines, the memory address corresponding to a single cache line in the set of cache lines, the apparatus maintaining a deferred list for the set of cache lines and a set of lists, each member of the set of lists corresponding to one cache line in the set of cache lines;
- and
- processing circuitry configured to:
- test the deferred list to determine that the deferred list is not empty;
- and
- place the request in the deferred list.
A method comprising:
- receiving a request at a memory device, the request indicating a memory address corresponding to a set of cache lines, the memory address corresponding to a single cache line in the set of cache lines, the memory device maintaining a deferred list for the set of cache lines and a set of lists, each member of the set of lists corresponding to one cache line in the set of cache lines;
- testing the deferred list to determine that the deferred list is not empty;
- and
- placing the request in the deferred list.
A non-transitory machine readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations comprising:
- receiving a request at a memory device, the request indicating a memory address corresponding to a set of cache lines, the memory address corresponding to a single cache line in the set of cache lines, the memory device maintaining a deferred list for the set of cache lines and a set of lists, each member of the set of lists corresponding to one cache line in the set of cache lines;
- testing the deferred list to determine that the deferred list is not empty;
- and
- placing the request in the deferred list.
Dependencies are inferred from the claim text.