Error rates for memory with built in error correction and detection
AssigneeMicrosoft Technology Licensing, LLC
InventorMonish Shah
Life of this patent
Estimating the term…
Abstract
The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.
Claims18
A method, comprising:
- receiving a write request to write data in a plurality of memory chips with built in error detection, wherein a number of memory chips included in the plurality of memory chips is based on a channel width for a data payload and a bit-width for each memory chip of the plurality of memory chips;
- determining parity bits for the data;
- storing the data in a subset of the plurality of memory chips, wherein storing the data in the subset of the plurality of memory chips is based on the bit-width for each memory chip;
- and
- storing the parity bits in one memory chip of the plurality of memory chips, wherein the one memory chip is different from the subset of the plurality of memory chips.
A method, comprising:
- receiving a write request to write data in one memory chip of a plurality of memory chips with built in error detection, wherein a number of memory chips included in the plurality of memory chips is based on a channel width for a data payload and a bit-width for each memory chip of the plurality of memory chips;
- determining a parity bit for the one memory chip;
- storing the data in the one memory chip, wherein storing the data in the subset of the plurality of memory chips is based on the bit-width for each memory chip;
- and
- storing the parity bit in the one memory chip.
A method, comprising:
- receiving a read request for data, wherein a subset of a plurality of memory chips with built in error detection stores the data;
- receiving, in response to the read request, the data from the subset of the plurality of memory chips and parity bits from one memory chip of the plurality of memory chips, wherein the one memory chip is different form the subset of the plurality of memory chips;
- and
- generating recovered data using the parity bits in response to receiving an error notification from a memory chip of the plurality of memory chips indicating that an uncorrectable error (UE) occurred with corrupted data, wherein generating the recovered data includes performing an exclusive OR operation with the parity bits and the data from the plurality of memory chips that did not send the error notification and adding a one or a zero for a bit of the recovered data for the memory chip to result in an even parity where an even number of inputs are true in response to the exclusive OR operation.
Dependencies are inferred from the claim text.