Redundant array management techniques
AssigneeMicron Technology, Inc.
InventorsChun Sum Yeung, Jonathan S. Parry, Deping He, Xiangang Luo, Reshmi Basu
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AssigneeMicron Technology, Inc.
InventorsChun Sum Yeung, Jonathan S. Parry, Deping He, Xiangang Luo, Reshmi Basu
Estimating the term…
Methods, systems, and devices for redundant array management techniques are described. A memory system may include a volatile memory device, a non-volatile memory device, and one or more redundant arrays of independent nodes. The memory system may include a first redundant array controller and a second redundant array controller of a redundant array of independent nodes. The memory system may receive a write command associated with writing data to a type of memory cell. Based on the type of memory cell, the memory system may generate parity data corresponding to the data using one or both of the first redundant array controller and the second redundant array controller. In some examples, the first redundant array controller may be configured to generate parity data associated with a first type of failure and the second redundant array controller may be configured to generate parity data associated with a second type of failure.
A memory system, comprising:
A memory system, comprising:
A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of a memory system, cause the memory system to:
Dependencies are inferred from the claim text.