US 12,111,680 B2 · Memory device including receiving circuit, electronic device, and received signal processing method of electronic device

Abstract

A memory device including a receiving circuit is provided. The receiving circuit of the memory device includes a first path receiving a received signal and outputting the received signal directly as a first corrected signal in a current clock signal, a second path holding or tracking the received signal and outputting a second corrected signal in the current clock signal, wherein the second corrected signal is held in a previous clock signal, a summing circuit summing the first corrected signal and the second corrected signal and outputting a summed received signal, and a decision feedback equalizer comparing the summed received signal with a reference signal to decide equalized data and outputting the equalized data in the current clock signal.

Claims20

Dependent claims

A memory device, comprising:

a receiving circuit, the receiving circuit including:
a first path receiving a received signal, and outputting the received signal directly as a first corrected signal in a current clock signal;
a second path holding or tracking the received signal, and outputting a second corrected signal in the current clock signal,
wherein the second corrected signal is held in a previous clock signal;
a summing circuit summing the first corrected signal and the second corrected signal, and outputting a summed received signal;
and
a decision feedback equalizer comparing the summed received signal with a reference signal to decide equalized data, and outputting the equalized data in the current clock signal.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/871,374Filed 22 Jul 2022

Priority

KR 10-2021-01524278 Nov 2021

Published

US 2023/0140969 A111 May 2023

Granted

8 Oct 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
H04L 25/03146
Non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals: with a recursive structure
H04L 25/03057
Adaptive, i.e. capable of adjustment during data reception: with a recursive structure
G06F
Computing and data processing

Memory device including receiving circuit, electronic device, and received signal processing method of electronic device

Life of this patent

Memory device including receiving circuit, electronic device, and received signal processing method of electronic device

Life of this patent

Abstract

Claims20