Clock control device and related products

An artificial intelligence chip that includes a device for clock control, comprising:

• a voltage detecting unit configured to detect a supply voltage at a target position in the processor, and output a voltage-alarm signal when the supply voltage is lower than or equal to a preset first threshold;
• and
• a clock stretching unit connected with the voltage detecting unit and configured to generate a second clock signal according to a first clock signal having a reference frequency in response to reception of the voltage-alarm signal, such that the processor uses the second clock signal to perform data processing, wherein a frequency of the second clock signal is lower than the reference frequency,
• wherein the voltage detecting unit includes a first detecting unit, wherein the first detecting unit includes:
• a pulse generation circuit configured to receive an input of a fifth clock signal and output a pulse signal,
• a delay circuit connected with the pulse generation circuit, and configured to receive an input of the pulse signal and output a delayed pulse signal, wherein a delay between the delayed pulse signal and the pulse signal is negatively correlated with the supply voltage at the target position, and
• a voltage detecting and processing circuit connected with the delay circuit, and configured to determine the supply voltage at the target position according to the delayed pulse signal and the fifth clock signal and output a first voltage-alarm signal when the supply voltage is lower than or equal to the first threshold.

An electronic device, wherein the electronic device comprises an artificial intelligence chip that includes a device for clock control, comprising:

• a voltage detecting unit configured to detect a supply voltage at a target position in the processor, and output a voltage-alarm signal when the supply voltage is lower than or equal to a preset first threshold;
• and
• a clock stretching unit connected with the voltage detecting unit and configured to generate a second clock signal according to a first clock signal having a reference frequency in response to reception of the voltage-alarm signal, such that the processor uses the second clock signal to perform data processing, wherein a frequency of the second clock signal is lower than the reference frequency,
• wherein the voltage detecting unit includes a first detecting unit, wherein the first detecting unit includes:
• a pulse generation circuit configured to receive an input of a fifth clock signal and output a pulse signal,
• a delay circuit connected with the pulse generation circuit, and configured to receive an input of the pulse signal and output a delayed pulse signal, wherein a delay between the delayed pulse signal and the pulse signal is negatively correlated with the supply voltage at the target position, and
• a voltage detecting and processing circuit connected with the delay circuit, and configured to determine the supply voltage at the target position according to the delayed pulse signal and the fifth clock signal and output a first voltage-alarm signal when the supply voltage is lower than or equal to the first threshold.

A device for clock control, being applied to a processor and comprising:

• a voltage detecting unit configured to detect a supply voltage at a target position in the processor, and output a voltage-alarm signal when the supply voltage is lower than or equal to a preset first threshold;
• and
• a clock stretching unit connected with the voltage detecting unit and configured to generate a second clock signal according to a first clock signal having a reference frequency in response to reception of the voltage-alarm signal, such that the processor uses the second clock signal to perform data processing, wherein
• a frequency of the second clock signal is lower than the reference frequency,
• wherein the clock stretching unit includes:
• a clock phase generation circuit configured to output a plurality of phase clock signals according to the first clock signal, and
• a clock stretching circuit connected with the clock phase generation circuit, and configured to generate the second clock signal through an integrated clock gating according to the plurality of phase clock signals in response to reception of the voltage-alarm signal.