System and method for access control of a plurality of instruments embedded in a semiconductor device

A method for testing a semiconductor device, the method comprising:

• configuring a test by defining interconnections of a plurality of instruments in the semiconductor device, wherein the instruments are reconfigurable scan networks, using an instrument connectivity language and defining operations of the instruments using a procedural description language;
• accessing access a control mechanism for controlling the plurality of instruments through a hardware interface to test at least one functionality of each of a plurality of instruments, thereby receiving a fault status of each of the plurality of instruments;
• configuring a test block in the semiconductor device to automatically exclude faulty hardware parts for specific instruments by using a repair component based on the fault status of the plurality of instruments, or excluding a procedural description language command specifically related to the faulty hardware parts;
• and
• performing a full test using all the plurality of instruments in the semiconductor device without updating the defined interconnections and operations of the instruments in the test.

A method for accessing a plurality of instruments embedded in a semiconductor device, wherein the instruments are reconfigurable scan networks, the method comprising the steps of:

• providing a hardware interface, such as a test access port or a functional port, configured to access a control mechanism for controlling the plurality of instruments;
• providing a test controller for testing the semiconductor device and generating test patterns for the semiconductor device, wherein the test controller comprises an instrument connectivity language and a procedural description language configuration for operating the instruments;
• testing at least one functionality of each of the plurality of instruments by accessing the control mechanism for controlling the plurality of instruments through the hardware interface, thereby receiving a fault status of each of the plurality of instruments;
• and
• based on the fault status of the plurality of instruments, configure a test block in the semiconductor device such that valid test patterns for the semiconductor device can be generated without updating the instrument connectivity language and procedural description language configuration by using a repair component to automatically exclude specific faulty scan registers from a scan-path in the scan testing.