US 12,111,348 B2Granted

Evaluation module and evaluation method for evaluating multichip module lifespan

AssigneesRobert Bosch GmbH, Huazhong University of Science and Technology

InventorsLin Liang, Lubin Han, Yong Kang, Xudan Liu, Maojun He

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Abstract

An evaluation module configured to evaluate the lifespan of a multichip module, the multichip module comprising a first substrate and multiple chips under evaluation, includes a second substrate, configured to be the same as the first substrate, and having attachment positions corresponding to the attachment positions on the first substrate, and at least one evaluation chip, configured to be the same as the multiple chips under evaluation. The number of evaluation chips is less than the number of chips under evaluation by at least one. The at least one evaluation chip is arranged at an attachment position on the second substrate, such that the at least one evaluation chip and the chip under evaluation arranged at the corresponding attachment position on the multichip module have the same cooling performance and sustain the same thermal stress. The present disclosure also discloses a method for evaluating the lifespan of a multichip module.

Claims17

Dependent claims

An evaluation module configured to evaluate the lifespan of a multichip module, the multichip module including a first substrate and multiple chips under evaluation arranged at at least one attachment position on the first substrate, comprising:

a second substrate configured to be the same as the first substrate of the multichip module, and having at least one attachment position, each of the at least one attachment position corresponding to a corresponding one of the at least one attachment position on the first substrate of the multichip module;
and
at least one evaluation chip configured to be the same as the multiple chips under evaluation of the multichip module, wherein:
the number of the at least one evaluation chip is less than the number of the multiple chips under evaluation of the multichip module by at least one;
and
the at least one evaluation chip is arranged at at least one of the at least one attachment position on the second substrate such that the at least one evaluation chip and the chip under evaluation arranged at the corresponding one of the at least one attachment position of the first substrate on the multichip module have the same cooling performance and sustain the same thermal stress during evaluation.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/483,411Filed 23 Sep 2021
Priority: CN 202011038511.428 Sep 2020
Published: US 2022/0099731 A131 Mar 2022
Granted: 8 Oct 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification16 codes

G01R 31/2855
Testing of integrated circuits [IC]: environmental, reliability or burn-in testing
G01R 31/2874
Related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation: related to temperature
H10D 62/8325
Being Group IV materials comprising two or more elements, e.g. SiGe: silicon carbide
H10P 74/277
Structural arrangements therefor: circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or…

Family

US 2022/0099731 A1Pre-grant publication · published 31 Mar 2022
US 12,111,348 B2This patent

From the US filing history. Foreign family members aren’t listed.

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