Applications of adaptive microelectronic circuits that are designed for testability

A microelectronic circuit comprising:

• a processing path, said processing path comprising circuit elements such as processing logic and register circuits, and said processing path being adaptively responsive to values of operating parameters made available to said circuit elements,
• a test input arrangement configured to controllably feed test input signals consisting of test input values into a plurality of circuit elements of said processing path,
• a test output arrangement configured to controllably collect test output values from said plurality of circuit elements of said processing path, and
• an operating parameter value selector configured to select said values of said operating parameters on the basis of said collected test output values.

A register circuit for temporarily storing a digital value obtained from an output of a preceding circuit element in a microelectronic circuit, the register circuit comprising:

• a data input for receiving said digital value for temporary storage,
• a data output for outputting the temporarily stored digital value,
• a triggering event input for receiving a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become temporarily stored, and
• on the data propagation path between said data input and data output a sequence of a first subregister stage and second subregister stage;
• wherein said first subregister stage is configured to receive said triggering signal delayed with respect to the triggering signal received by said second subregister stage, the length of the delay being a fraction of a cycle of said triggering signal,
• and wherein said register circuit comprises a timing event observation logic configured to output a timing event observation signal at an output of said register circuit as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal,
• and wherein said register circuit is adaptively responsive to values of operating parameters made available to said register circuit.

A monitor circuit for detecting timing events in a register circuit of a microelectronic circuit, the monitor circuit comprising:

• a triggering event input for receiving a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at a data input of said register circuit to become temporarily stored in said register circuit,
• a monitoring input for receiving a monitoring copy of said digital value at the same timing as at which said digital value appears at said data input of said register circuit,
• a timing event observation output, and
• a timing event observation logic configured to output a timing event observation signal at said timing event observation output as an indicator of said digital value at said data input having changed within a time window that begins at said allowable time limit and is shorter than one cycle of said triggering signal;
• wherein the monitor circuit comprises an output handling unit configured to enable collecting values of said timing event observation signal for further processing outside the monitor circuit, and wherein said monitor circuit is adaptively responsive to values of operating parameters made available to said monitor circuit.