Memory device deserializer circuit with a reduced form factor
AssigneeMicron Technology, Inc.
InventorsGuan Wang, Luigi Pilolli
Life of this patent
Estimating the term…
Abstract
A memory sub-system including a memory device, wherein the memory device includes a circuit, operatively coupled to an array data bus of a memory array, and control logic, operatively coupled with the circuit, to perform operations including: deserializing a serial data stream in a first time domain to generate at least one of a set of rising data portions or a set of falling data portions; and synchronizing the at least one of the set of rising data portions or the set of falling data portions in a second time domain using at least one of a set of rising edge clock signals or a set of falling edge clock signals generated by a ring counter portion.
Claims20
A memory sub-system comprising:
- a memory device comprising a circuit operatively coupled to an array data bus of a memory array;
- and
- control logic, operatively coupled with the circuit, to perform operations comprising:
- deserializing a serial data stream in a first time domain to generate at least one of a set of rising data portions or a set of falling data portions;
- and
- synchronizing the at least one of the set of rising data portions or the set of falling data portions in a second time domain using at least one of a set of rising edge clock signals or a set of falling edge clock signals generated by a ring counter portion.
A memory sub-system comprising:
- a memory device comprising a circuit operatively coupled to an array data bus of a memory array;
- and
- control logic, operatively coupled with the circuit, to perform operations comprising:
- deserializing a serial data stream in a first time domain to generate a set of rising data portions;
- and
- synchronizing the set of rising data portions in a second time domain using a set of rising edge clock signals generated by a ring counter portion.
A memory sub-system comprising:
- a memory device comprising a circuit operatively coupled to an array data bus of a memory array;
- and
- control logic, operatively coupled with the circuit, to perform operations comprising:
- deserializing a serial data stream in a first time domain to generate a set of falling data portions;
- and
- synchronizing the set of falling data portions in a second time domain using a set of falling edge clock signals generated by a ring counter portion.
Dependencies are inferred from the claim text.