Oscillator monitoring circuits for different oscillator domains

A clock monitor for a monitored circuit having a plurality of oscillators, the clock monitor comprising:

• means for synchronization configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
• a counter configured to produce a count value based on synchronized clock signal;
• and
• comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
• wherein the first oscillator is configured to run at a nominal frequency of about 250 kHz and the second oscillator is configured to run at a nominal frequency of about 2 MHz, wherein the means for synchronization is disposed in a domain of the second oscillator.

A clock monitor for a monitored circuit having a plurality of oscillators, the clock monitor comprising:

• means for synchronization configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
• a counter configured to produce a count value based on synchronized clock signal;
• and
• comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
• wherein the first oscillator is configured to run at a nominal frequency of about 250 kHz and the second oscillator is configured to run at a nominal frequency of about 16 MHz, wherein the means for synchronization is disposed in a domain of the second oscillator.

A clock monitor for a monitored circuit having a plurality of oscillators, the clock monitor comprising:

• means for synchronization configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
• a counter configured to produce a count value based on synchronized clock signal;
• and
• comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
• wherein the first oscillator is configured to run at a nominal frequency of about 2 MHz and the second oscillator is configured to run at a nominal frequency of about 250 kHz, wherein the means for synchronization is disposed in the domain of the second oscillator.

A clock monitor circuit for detecting oscillator frequency error in an integrated circuit including a plurality of oscillators, the clock monitor circuit comprising:

• a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
• a counter configured to produce a count value based on synchronized clock signal;
• and
• comparison means configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
• wherein the first oscillator is configured to run at a nominal frequency of about 2 MHz and the second oscillator is configured to run at a nominal frequency of about 16 MHz, wherein the synchronizer is disposed in a domain of the second oscillator.

A clock monitor circuit for detecting oscillator frequency error in an integrated circuit including a plurality of oscillators, the clock monitor circuit comprising:

• a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
• a counter configured to produce a count value based on synchronized clock signal;
• and
• comparison means configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
• wherein the first oscillator is configured to run at a nominal frequency of about 250 kHz and the second oscillator is configured to run at a nominal frequency of about 2 MHz, wherein the synchronizer is disposed in a domain of the second oscillator.

A clock monitor circuit for detecting oscillator frequency error in an integrated circuit including a plurality of oscillators, the clock monitor circuit comprising:

• a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
• a counter configured to produce a count value based on synchronized clock signal;
• and
• comparison means configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
• wherein the first oscillator is configured to run at a nominal frequency of about 250 kHz and the second oscillator is configured to run at a nominal frequency of about 16 MHz, wherein the synchronizer is disposed in a domain of the second oscillator.

A clock monitor circuit for detecting oscillator frequency error in an integrated circuit including a plurality of oscillators, the clock monitor circuit comprising:

• a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator of the plurality of oscillators and to produce a synchronized clock signal;
• a counter configured to produce a count value based on synchronized clock signal;
• and
• comparison means configured to receive the count value and produce an error indication when the count value is outside a predetermined range;
• wherein the first oscillator is configured to run at a nominal frequency of about 2 MHz and the second oscillator is configured to run at a nominal frequency of about 250 kHz, wherein the synchronizer is disposed in the domain of the second oscillator.