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US 12,063,041 B2Granted
Flip flop standard cell
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsNick Samra, Stefan Rusu, Ta-Pen Guo
Life of this patent
Estimating the term…
Abstract
A flip flop standard cell that includes a data input terminal configured to receive a data signal, clock input terminal configured to receive a clock signal, a data output terminal, and a latch. A bit write circuit is configured to receive a bit write signal. The received data signal is latched and provided at the output terminal in response to the bit write signal and the clock signal. A hold circuit is configured to receive a hold signal, and the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal.
Claims20
A flip flop standard cell, comprising:
- a data input terminal;
- clock input terminal configured to receive a clock signal;
- a data output terminal;
- a latch;
- a bit write circuit configured to receive a bit write signal, wherein the received data signal is latched and provided at an output terminal in response to the bit write signal and the clock signal;
- and
- a hold circuit configured to receive a hold signal, wherein the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal;
- a scan input terminal configured to receive a scan data signal;
- a scan enable terminal configured to receive a scan enable signal, wherein a received data signal is not provided at the data output terminal, and the scan data signal is provided at the output terminal in response to the scan input signal and the clock signal;
- and
- the scan enable transistor having a gate terminal, an input terminal, and an output terminal, wherein the gate terminal is connected to the scan enable terminal, the input terminal is connected to the scan input terminal, and the output terminal is connected to the latch, such that the scan data signal received at the scan input terminal is output to the latch in response to the scan enable signal received at the scan enable terminal.
8 more elements
A flip flop standard cell, comprising:
- a data input terminal;
- clock input terminal configured to receive a clock signal;
- a data output terminal;
- a latch;
- a bit write circuit comprising a bit write transistor having a gate terminal, an input terminal, and an output terminal, wherein the gate terminal is connected to the bit write terminal, the input terminal is connected to the data input terminal, and the output terminal is connected to the latch, such that a received data signal is output to the latch in response to a bit write signal received at the bit write terminal and a clock signal;
- a hold circuit configured to receive a hold signal, wherein the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal;
- a scan input terminal configured to receive a scan data signal;
- and
- a scan enable terminal configured to receive a scan enable signal, wherein a received data signal is not provided at the data output terminal, and the scan data signal is provided at the output terminal in response to the scan input signal and the clock signal.
6 more elements
A flip flop standard cell, comprising:
- a data input terminal;
- clock input terminal configured to receive a clock signal;
- a data output terminal;
- a latch;
- a bit write circuit configured to receive a bit write signal, wherein the received data signal is latched and provided at an output terminal in response to the bit write signal and the clock signal;
- and
- a hold circuit configured to receive a hold signal, wherein the received data signal is not latched and provided at the data output terminal in response to the hold signal and the clock signal, the hold circuit including a hold transistor having a gate terminal, an input terminal, and an output terminal, wherein the gate terminal is connected to a hold terminal of the flip flop standard cell, the input terminal is connected to the data output terminal, and the output terminal is connected to the latch, such that an output data signal at the data output terminal is fed back to the latch in response to the hold signal received at the hold terminal;
- a scan input terminal configured to receive a scan data signal;
- and
- a scan enable terminal configured to receive a scan enable signal, wherein a received data signal is not provided at the data output terminal, and the scan data signal is provided at the output terminal in response to the scan input signal and the clock signal.
7 more elements
Dependencies are inferred from the claim text.