Display substrate and manufacturing method thereof, display panel, and display device

A manufacturing method of a display substrate, comprising:

• providing a base substrate comprising a display area and a peripheral area located on at least a first side of the display area;
• forming a plurality of pixel units in the display area of the base substrate, wherein the plurality of pixel units are arranged in an array in a first direction and a second direction in the display area of the base substrate, and each of the plurality of pixel units comprises a pixel drive circuit;
• forming a planarization layer on a side of the pixel units away from the base substrate, wherein at least a portion of the planarization layer is located in the peripheral area;
• forming a plurality of light-emitting devices on the base substrate, wherein each of the plurality of light-emitting devices is electrically connected to a respective one of the pixel drive circuits of the plurality of pixel units, and each of the plurality of light-emitting devices comprises a first electrode, a second electrode, and a light-emitting layer between the first electrode and the second electrode;
• forming a first power trace and a second power trace in the peripheral area of the base substrate;
• and
• forming a frame sealant in the peripheral area of the base substrate,
• wherein the peripheral area comprises a first peripheral area on a side of the frame sealant close to the display area and a second peripheral area on a side of the frame sealant away from the display area, the first side of the display area is a signal input side, and the first power trace and the second power trace are both located in the first peripheral area and on the signal input side, and an orthographic projection of each of the first power trace and the second power trace on the base substrate does not overlap with an orthographic projection of the frame sealant on the base substrate;
• wherein the first power trace is electrically connected to the first electrode, and the second power trace is electrically connected to the second electrode;
• and
• wherein an orthographic projection of each of the first power trace and the second power trace on the base substrate falls within an orthographic projection of the planarization layer on the base substrate, the first power trace and the second power trace are located in different layers, and a portion of the planarization layer is located between the first power trace and the second power trace.