Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of semiconductor patterns extending, above a substrate, in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including
• a first source/drain area,
• a channel area, and
• a second source/drain area arranged in the first horizontal direction;
• a plurality of gate insulating layers covering upper surfaces or side surfaces of the channel areas of the plurality of semiconductor patterns;
• a plurality of word lines on the upper surfaces or the side surfaces of the channel areas of the plurality of semiconductor patterns;
• and
• a plurality of resistive switch units respectively connected to first sidewalls of the plurality of semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including
• a first electrode,
• a second electrode, and
• a resistive switch material layer between the first electrode and the second electrode,
• wherein the resistive switch material layer includes a carbon nanotube bundle and is configured to transit from a high resistance state to a low resistance state when a set voltage is applied to the plurality of resistive switch units.

A semiconductor memory device comprising:

• a plurality of semiconductor patterns extending, above a substrate, in a first horizontal direction and separated from each other in a second horizontal direction and a vertical direction, each semiconductor pattern including
• a first source/drain area,
• a channel area, and
• a second source/drain area arranged in the first horizontal direction;
• a plurality of gate insulating layers covering lower surfaces and upper surfaces of the channel areas of the plurality of semiconductor patterns;
• a plurality of word lines on the lower surfaces and the upper surfaces of the channel areas of the plurality of semiconductor patterns, extending in the second horizontal direction, and extending in the vertical direction;
• a plurality of resistive switch units respectively connected to first sidewalls of the plurality of semiconductor patterns, extending in the first horizontal direction, and separated from each other in the second horizontal direction and the vertical direction, each resistive switch unit including
• a first electrode,
• a second electrode, and
• a resistive switch material layer between the first electrode and the second electrode, the resistive switch material layer including a carbon nanotube bundle;
• and
• a plurality of bit lines connected to second sidewalls of the plurality of semiconductor patterns, extending in the vertical direction, and separated from each other in the second horizontal direction.