US 12,016,185 B1Granted

Planar and trench capacitors for logic and memory applications

AssigneeKepler Computing Inc.

InventorsSomilkumar J. Rathi, Noriyuki Sato, Niloy Mukherjee, Rajeev Kumar Dokania, Amrita Mathuriya, Tanay Gosavi, Pratyush Pandey, Jason Y. Wu, Sasikanth Manipatruni

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Abstract

A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

Claims20

Dependent claims

A device comprising:

a first electrode structure and a second electrode structure within an etch stop layer comprising an insulator, the first electrode structure laterally separated from the second electrode structure, wherein the first electrode structure and the second electrode structure comprise:
a first conductive hydrogen barrier layer, and
a first conductive fill material on the first conductive hydrogen barrier layer;
a planar capacitor comprising a first ferroelectric material or a first paraelectric material on least a portion of the first electrode structure;
an encapsulation layer on the planar capacitor,
a dielectric on the encapsulation layer;
a via electrode on at least a portion of the planar capacitor, the via electrode comprising:
a second conductive hydrogen barrier layer;
and
a second conductive fill material on the second conductive hydrogen barrier layer,
a trench within the dielectric, the trench on the second electrode structure;
a spacer along a sidewall of the trench;
and
a non-planar capacitor within the trench, the non-planar capacitor comprising:
a bottom electrode that is substantially conformal along a base of the trench and the spacer, wherein the bottom electrode is in contact with the second electrode structure;
a dielectric layer substantially conformal to the bottom electrode, the dielectric layer comprising a second ferroelectric material or a second paraelectric material;
and
a top electrode in contact with the dielectric layer.

15 more elements

A device comprising:

a first electrode structure and a second electrode structure within an etch stop layer comprising an insulator, the first electrode structure laterally separated from the second electrode structure, wherein the first electrode structure and the second electrode structure comprise:
a first conductive hydrogen barrier layer, and
a first conductive fill material on the first conductive hydrogen barrier layer;
a planar capacitor comprising a first ferroelectric material or a first paraelectric material on least a portion of the first electrode structure;
a dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material on the planar capacitor and on the etch stop layer;
a via electrode on at least a portion of the planar capacitor, the via electrode comprising:
a second conductive hydrogen barrier layer;
and
a second conductive fill material on the second conductive hydrogen barrier layer,
a trench within the dielectric, the trench on the second electrode structure;
and
a non-planar cylindrical capacitor within the trench, the non-planar cylindrical capacitor comprising:
a bottom electrode that is substantially conformal along a base and sidewall of the trench, wherein the bottom electrode is in contact with the second electrode structure;
a dielectric layer substantially conformal to the bottom electrode, the dielectric layer comprising a second ferroelectric material or a second paraelectric material;
and
a top electrode in contact with the dielectric layer.

13 more elements

A device comprising:

a first electrode structure and a second electrode structure within an etch stop layer comprising an insulator, the first electrode structure laterally separated from the second electrode structure, wherein the first electrode structure and the second electrode structure comprise:
a first conductive hydrogen barrier layer, and
a first conductive fill material on the first conductive hydrogen barrier layer;
a planar capacitor comprising a first ferroelectric material or a first paraelectric material on least a portion of the first electrode structure;
an encapsulation layer on the planar capacitor,
a dielectric on the encapsulation layer the dielectric comprising an amorphous, greater than 90% film density hydrogen barrier material;
a via electrode on at least a portion of the planar capacitor, the via electrode comprising:
a second conductive hydrogen barrier layer;
and
a second conductive fill material on the second conductive hydrogen barrier layer,
a trench within the dielectric, the trench on the second electrode structure;
and
a non-planar capacitor within the trench, the non-planar capacitor comprising:
a bottom electrode that is substantially conformal along a base and sidewall of the trench, wherein the bottom electrode is in contact with the second electrode structure and the encapsulation layer;
a dielectric layer substantially conformal to the bottom electrode, the dielectric layer comprising a second ferroelectric material or a second paraelectric material;
and
a top electrode in contact with the dielectric layer.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/552,293Filed 15 Dec 2021 · continuation
Priority: 14 Dec 2021
Granted: 18 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification23 codes

H10D 1/042
Of capacitors having no potential barriers: using deposition processes to form electrode extensions
H10B 51/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the memory core region
H10B 53/30
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors: characterised by the memory core region
H10D 1/043
Of capacitors having no potential barriers: using patterning processes to form electrode extensions, e.g. etching

Family

Application17/550,899Parent of this continuation · filed 14 Dec 2021
US 11,961,877 B1Related patent
US 12,016,185 B1This patent

From the US filing history. Foreign family members aren’t listed.

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