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US 12,016,183 B2Granted
Memory chip including control logic circuit with dynamic random-access memory and memory device including memory chips
AssigneeHon Hai Precision Industry Co., Ltd.
InventorYan-Ru Chen
Life of this patent
Estimating the term…
Abstract
A memory chip includes a memory cell circuit, a periphery circuit, an interconnect structure, and a control logic circuit. The periphery circuit is positioned under the memory cell circuit and electrically connected to the memory cell circuit. The interconnect structure is positioned on a side surface of the memory cell circuit. The control logic circuit is positioned under the interconnect structure. The control logic circuit is electrically connected to the interconnect structure and the periphery circuit and includes a dynamic random-access memory.
Claims8
A memory chip, comprising:
- a memory cell circuit;
- a periphery circuit positioned under the memory cell circuit and electrically connected to the memory cell circuit;
- an interconnect structure positioned on a side surface of the memory cell circuit;
- and
- a control logic circuit positioned under the interconnect structure, wherein the control logic circuit is electrically connected to the interconnect structure and the periphery circuit, the control logic circuit comprises a dynamic random-access memory, a reduced instruction set computer core, a memory controller, and an error correction circuit, the reduced instruction set computer core is connected to the memory controller and the dynamic random-access memory, the memory controller is electrically connected to the peripheral circuit, and the error correction circuit is connected to the memory controller.
2 more elements
A memory chip, comprising:
- a memory cell circuit;
- a periphery circuit positioned under the memory cell circuit and electrically connected to the memory cell circuit;
- an interconnect structure positioned on a side surface of the memory cell circuit;
- and
- a control logic circuit positioned under the interconnect structure, wherein the control logic circuit is electrically connected to the interconnect structure and the periphery circuit, the control logic circuit comprises a dynamic random-access memory, a reduced instruction set computer core, a memory controller, an interface circuit, and a power management circuit, the reduced instruction set computer core is connected to the memory controller and the dynamic random-access memory, the memory controller is electrically connected to the peripheral circuit, and the interface circuit is connected to the power management circuit and the reduced instruction set computer core and is connected to the interconnect structure.
2 more elements
Dependencies are inferred from the claim text.