Semiconductor device

A semiconductor device, comprising:

• a substrate including a cell array region and a peripheral circuit region;
• a cell transistor on the cell array region of the substrate;
• a peripheral transistor on the peripheral circuit region of the substrate;
• a first interconnection layer connected to the cell transistor;
• a second interconnection layer connected to the peripheral transistor;
• a first interlayer dielectric layer covering the first interconnection layer;
• and
• a second interlayer dielectric layer spaced apart from the first interconnection layer and covering the second interconnection layer,
• wherein a top surface of the first interlayer dielectric layer is coplanar with a top surface of the second interlayer dielectric layer, and
• wherein a material of the first interlayer dielectric layer is different from a material of the second interlayer dielectric layer.

A semiconductor device, comprising:

• a substrate including a cell array region and a peripheral circuit region;
• a plurality of cell transistors on the cell array region of the substrate;
• a plurality of capacitors on the plurality of cell transistors, each of the plurality of capacitors connected to a corresponding one of the plurality of cell transistors;
• a plurality of peripheral transistors on the peripheral circuit region of the substrate;
• a first lower interconnection layer connected to one of the plurality of capacitors;
• a second lower interconnection layer connected to one of the plurality of peripheral transistors;
• an interface layer covering the first lower interconnection layer and the second lower interconnection layer;
• a first upper interconnection layer connected to the first lower interconnection layer;
• a second upper interconnection layer connected to the second lower interconnection layer;
• a first interlayer dielectric layer covering the first upper interconnection layer;
• a second interlayer dielectric layer spaced apart from the first upper interconnection layer and covering the second upper interconnection layer;
• and
• a passivation layer on the first interlayer dielectric layer and the second interlayer dielectric layer,
• wherein the semiconductor device includes:
• a plurality of first impurity regions and a plurality of second impurity regions in an upper portion of an active section defined by a device isolation layer;
• a plurality of bit-line contacts connected to the plurality of first impurity regions;
• and
• a plurality of node contacts connected to the plurality of second impurity regions, and
• wherein each of the plurality of capacitors includes a bottom electrode, a top electrode, and a dielectric layer between the bottom electrode and the top electrode.