Fast-locking phase-locked loop, transceiver, and communication device

A fast-locking phase-locked loop, comprising a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a frequency divider, and further comprising:

• a fast-locking control unit that has a first input terminal for receiving a reference clock signal and a second input terminal for receiving a phase-locking enable signal and is configured to shift an outputted reset signal from a low level to a high level in response to a rising edge of the reference clock signal, when the received phase-locking enable signal is at a high level, so as to reduce an initial phase error between the reference clock signal and a feedback signal,
• wherein the frequency divider is connected to an output terminal of the fast-locking control unit and configured to trigger generation of the feedback signal in response to the reset signal at the high level;
• and
• the phase frequency detector is connected to the output terminal of the fast-locking control unit and configured to output a phase error between the reference clock signal and the feedback signal in response to the reset signal at the high level.