Transmitter circuit, corresponding isolated driver device, electronic system and method of encoding a pulse-width modulated signal into a differential pulsed signal

An isolated driver device, comprising:

• a first semiconductor die having a transmitter circuit implemented thereon, the transmitter circuit including:
• a first input node configured to receive a pulse-width modulated input signal;
• a second input node configured to receive a clock signal having a frequency higher than a frequency of said pulse-width modulated input signal;
• a logic circuit sensitive to said clock signal and configured to generate a control signal as a function of said clock signal, wherein said control signal is normally set to a first logic value, and is periodically set to a second logic value for a transmission time interval in response to an edge being detected in said clock signal, said transmission time interval being shorter than a half clock period of said clock signal;
• a tri-state transmitter coupled to the first input node to receive said pulse-width modulated input signal and sensitive to said control signal, the tri-state transmitter being configured to produce a first output signal at a first transmitter output node and a second output signal at a second transmitter output node, the first output signal and the second output signal having a voltage swing between a positive supply voltage and a reference supply voltage;
• an output control circuit sensitive to said control signal and coupled to said first transmitter output node and said second transmitter output node,
• wherein:
• in response to said control signal having said first logic value, said tri-state transmitter sets said first transmitter output node and said second transmitter output node to a high impedance state, and said output control circuit drives said first transmitter output node and said second transmitter output node to an intermediate voltage level between said positive supply voltage and said reference supply voltage;
• and
• in response to said control signal having said second logic value, said tri-state transmitter drives said first transmitter output node to said positive supply voltage or to said reference supply voltage according to the logic value of said pulse-width modulated input signal, and drives said second transmitter output node to said positive supply voltage or to said reference supply voltage according to an inverted logic value of said pulse-width modulated input signal,
• wherein said tri-state transmitter is faster than said output control circuit in driving said first transmitter output node and said second transmitter output node;
• and
• a second semiconductor die having a first receiver input node and a second receiver input node, the first receiver input node being electrically coupled to a first differential output node of the transmitter circuit and the second receiver input node being electrically coupled to a second differential output node of the transmitter circuit to receive a differential output signal,
• wherein the second semiconductor die has a receiver circuit implemented thereon, the receiver circuit being configured to receive said differential output signal, and to set a driving signal to a first logic value in response to a positive pulse being detected in said differential output signal and to a second logic value in response to a negative pulse being detected in said differential output signal.

A method of encoding a pulse-width modulated signal into a differential pulsed signal, the method comprising:

• receiving said pulse-width modulated signal;
• providing a clock signal having a frequency higher than the frequency of said pulse-width modulated signal;
• generating a control signal as a function of said clock signal, wherein said control signal is normally set to a first logic value, and is periodically set to a second logic value for a transmission time interval in response to an edge being detected in said clock signal, said transmission time interval being shorter than a half clock period of said clock signal;
• producing a first output signal and a second output signal, the first output signal and the second output signal having a voltage swing between a positive supply voltage and a reference supply voltage;
• and
• applying capacitive filtering to said first output signal and said second output signal to produce respective first and second filtered output signals, wherein said differential pulsed signal is produced as a difference between said first filtered output signal and said second filtered output signal,
• wherein producing said first output signal and said second output signal includes:
• in response to said control signal having said first logic value, setting said first output signal and said second output signal to an intermediate voltage level between said positive supply voltage and said reference supply voltage;
• and
• in response to said control signal having said second logic value, setting said first output signal to said positive supply voltage or to said reference supply voltage according to the logic value of a pulse-width modulated input signal, and setting said second output signal to said positive supply voltage or to said reference supply voltage according to an inverted logic value of said pulse-width modulated input signal,
• wherein a time interval for setting said first output signal and said second output signal to said positive supply voltage or to said reference supply voltage is shorter than a time interval for setting said first output signal and said second output signal to said intermediate voltage level.