Optical transmitter chip based on OTN transmission technology

An optical transmitter chip based on OTN transmission technology, characterized in that, comprising:

• a transmitter TX, a digital control unit DIGIITAL, and a power module POWER;
• the digital control unit DIGIITAL communicates with a host and provides a control signal to the transmitter TX;
• the power module POWER is arranged to provide working power to the chip;
• the transmitter TX first utilizes an optical modulation amplitude signal loss module OMALOS to complete a judgment of an optical modulation amplitude for an attenuated electrical signal transmitted through metal traces on a PCB board, wherein if the signal has a value greater than a preset threshold, the module outputs an enable signal to control a linear equalizer CTLE and a laser driver 28G VCSELDRIVER to start, and activate the chip to drive a VCSEL laser to emit an optical signal to open a signal transmission path;
• otherwise, the entire signal transmission path is closed;
• then, under a condition that the signal transmission path is open, the linear equalizer CTLE is utilized to complete a first stage optimization for high-frequency compensation of the attenuated electrical signal transmitted through the metal traces on the PCB board;
• specifically, one of the multi-rate clock data recovery module CDR and the signal bypass ByPass is selected as the selected signal path to start according to a judgment decision by:
• a first type:
• in FC mode, a fiber channel mode rate decision module FC_mode_Rate_decision is activated, if a signal detected by the fiber channel mode rate decision module FC_mode_Rate_decision is 8G FC, the fiber channel mode rate decision module FC_mode_Rate_decision controls to activate the signal bypass ByPass as the selected signal path;
• if a signal detected by the fiber channel mode rate decision module FC_mode_Rate_decision is 16G/32G FC, the fiber channel mode rate decision module FC_mode_Rate_decision controls to activate the multi-rate clock data recovery module CDR as the selected signal path;
• a second type:
• in non-FC mode, the signal bypass ByPass is the signal path with a signal rate is 1˜28.1 Gbps;
• the multi-rate clock data recovery module CDR supports the signal path with a 19˜28.1 Gbps signal rate or the signal path with a 19/2˜28.1/2 Gbps signal rate, the signal path and a clock rate selection are configured by a digital register;
• and then, a second stage optimization of the signal is processed, specifically:
• process judgment of the signal after the first stage optimization, and according to the judgment decision, select one of a multi-rate clock data recovery module CDR and a signal bypass ByPass as a selected signal path to start;
• if the multi-rate clock data recovery module CDR is started, a signal quality of the signal after the first stage optimization is further improved to complete the second stage optimization;
• the signal after a two-stage optimization is sent to the laser driver 28G VCSELDRIVER to drive the VCSEL laser to emit an optical signal.