MAC processing pipeline using filter weights having enhanced dynamic range, and methods of operating same

An integrated circuit comprising:

• a first memory to store a plurality of sets of filter weights;
• first data format conversion circuitry having:
• inputs to receive the plurality of sets of filter weights from the first memory, wherein each of the sets of filter weights includes a plurality of filter weights having a block-scaled fraction data format;
• Winograd conversion circuitry, coupled to the inputs of the first data format conversion circuitry, to convert each of the sets of filter weights to a corresponding Winograd set of filter weights;
• floating point format conversion circuitry, coupled to the Winograd conversion circuitry, to convert the filter weights of each Winograd set of filter weights to a floating point data format;
• and
• outputs to output the filter weights of each Winograd set of filter weights having the floating point data format;
• a second memory coupled to the outputs of the first data format conversion circuitry to receive and store the filter weights of each Winograd set of filter weights having the floating point data format;
• and
• a multiplier-accumulator execution pipeline having a plurality of multiplier-accumulator circuits, each of the multiplier-accumulator circuits having:
• first inputs to receive image data;
• second inputs coupled to the second memory to receive a respective one of the Winograd sets of filter weights having the floating point data format;
• and
• multiply-accumulate circuitry to generate output data by performing multiply and accumulate operations using the image data received via the first inputs and the respective one of the Winograd sets of filter weights received via the second inputs.