Dual digital phase lock loop with unmodulation coupling
AssigneeRenesas Electronics America Inc.
InventorMenno Tjeerd Spijker
Life of this patent
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Abstract
Semiconductor devices for synchronizing networks are described. A semiconductor device can include an analog phase-lock loop (APLL) configured to output a first signal. The semiconductor device can further include a first digital phase-lock loop (DPLL) configured to output a second signal. The semiconductor device can further include a second DPLL configured to output a third signal. A combination of the first signal and the second signal can be used to generate a first output clock signal. A difference resulting from a subtraction of the second signal from the third signal can be used to generate a second output clock signal.
Claims20
A semiconductor device comprising:
- an analog phase-lock loop (APLL) configured to output a first signal;
- a first digital phase-lock loop (DPLL) configured to output a second signal;
- and
- a second DPLL configured to output a third signal, wherein:
- a combination of the first signal and the second signal is being used to generate a first output clock signal;
- and
- a difference resulting from a subtraction of the second signal from the third signal is being used to generate a second output clock signal.
An apparatus comprising:
- a plurality of transceivers;
- a timing circuit configured to:
- receive a first reference signal from a first transceiver among the plurality of transceivers;
- receive a second reference signal from a second transceiver among the plurality of transceivers;
- output a first output clock signal to a second transceiver among the plurality of transceivers;
- and
- output a second output clock signal to a second clock circuit among the plurality of clock circuits,
- wherein:
- the first output clock signal is based on a combination of a first signal generate by an analog phase-lock loop (APLL) and a second signal generated by a first digital phase-lock loop (DPLL) in the timing circuit;
- and
- the second output clock signal is based on a difference resulting from a subtraction of the second signal from a third signal generates by a second DPLL of the timing circuit.
A method for operating a timing circuit to synchronize a plurality of networks, the method comprising:
- operating an analog phase-lock loop (APLL) to output a first signal;
- operating a first digital phase-lock loop (DPLL) to output a second signal;
- operating a second DPLL to output a third signal;
- combining the first signal and the second signal to generate a first output clock signal;
- and
- subtracting the second signal from the third signal to generate a second output clock signal, wherein the second output clock signal is independent from operations of the first DPLL.
Dependencies are inferred from the claim text.