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US 12,015,411 B2Granted
Testable time-to-digital converter
AssigneeSynopsys, Inc.
InventorsEmil Gizdarski, Anubhav Sinha
Life of this patent
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Abstract
A delay selector includes a first multiplexer, a first inverter, a second multiplexer, and a second inverter. The first multiplexer has a first input coupled to an input of the delay selector. The first inverter is coupled between the input of the delay selector and a second input of the first multiplexer. The second multiplexer has a first input coupled to an output of the first multiplexer. The second inverter is coupled between the output of the first multiplexer and a second input of the second multiplexer.
Claims20
A delay selector, comprising:
- a first multiplexer having a first input coupled to an input of the delay selector;
- a first inverter coupled between the input of the delay selector and a second input of the first multiplexer;
- a second multiplexer having a first input coupled to an output of the first multiplexer;
- and
- a second inverter coupled between the output of the first multiplexer and a second input of the second multiplexer.
2 more elements
A time-to-digital converter (TDC) comprising:
- a delay selector comprising:
- a first multiplexer having a first input coupled to an input of the delay selector;
- a first inverter coupled between the input of the delay selector and a second input of the first multiplexer;
- a second multiplexer having a first input coupled to an output of the first multiplexer;
- and
- a second inverter coupled between the output of the first multiplexer and a second input of the second multiplexer;
- and
- a first flip flop having an input coupled to an output of the delay selector.
5 more elements
A TDC comprising:
- a delay selector comprising:
- a first multiplexer having a first input coupled to an input of the delay selector;
- a first inverter coupled between the input of the delay selector and a second input of the first multiplexer;
- a second multiplexer having a first input coupled to an output of the first multiplexer;
- and
- a second inverter coupled between the output of the first multiplexer and a second input of the second multiplexer;
- a third multiplexer arranged to receive an output of the delay selector at a first input of the third multiplexer;
- and
- a first flip flop coupled to an output of the third multiplexer.
6 more elements
Dependencies are inferred from the claim text.