Semiconductor device with daisy-chained delay cells and method of forming same

A semiconductor device, comprising:

• a first dummy group that includes a first set of dummy transistors;
• a first delay cell that includes a first set of active transistors;
• a second delay cell that includes a second set of active transistors;
• a second dummy group that includes a second set of dummy transistors;
• the first and second dummy groups and the first and second delay cells being arranged in a first row that extends in a first direction;
• relative to the first direction:
• the first row having a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group;
• and
• the first and second delay cells being free from another dummy group therebetween;
• a third dummy group that includes a third set of dummy transistors;
• a first portion of a third delay cell that includes a third set of active transistors of a first conductivity-type;
• a first portion of a fourth delay cell that includes a fourth set of active transistors of the first conductivity-type;
• a fourth dummy group that includes a fourth set of dummy transistors;
• relative to the first direction:
• first portions of the third and fourth dummy groups and the first portions of the third and fourth delay cells being arranged in a first layer of a second row;
• and
• the second row having a second sequence arranged as the third dummy group, the first portion of the third delay cell, the first portion of the fourth delay cell, and the fourth dummy group;
• the third and fourth delay cells being free from another dummy group therebetween;
• second portions of the third and fourth dummy groups being arranged in a second layer of the second row;
• and
• relative to a second direction perpendicular to the first direction, the second row abutting the first row.

A semiconductor device, comprises:

• a first dummy group defined by one or more corresponding dummy transistors;
• a second dummy group defined by one or more corresponding dummy transistors;
• a first delay cell defined by one or more corresponding active transistors;
• a second delay cell defined by one or more corresponding active transistors;
• a batch of N delay cells, where N is a positive integer, defined by a batch of N sets of active transistors;
• relative to a first direction:
• the first and second dummy groups and the first and second delay cells being in a first row that extends in the first direction, the first row having an open first sequence arranged as the first dummy group, the first delay cell, the batch of N delay cells, the second delay cell, and the second dummy group;
• the batch of N delay cells is in the first row;
• and
• the first and second delay cells being free from having another dummy group therebetween;
• a third dummy group defined by one or more corresponding dummy transistors;
• a fourth dummy group defined by one or more corresponding dummy transistors;
• and
• relative to the first direction:
• the third and fourth dummy groups being in a second row that extends in the first direction;
• and
• relative to a second direction perpendicular to the first direction:
• the second row abutting the first row;
• the first dummy group overlapping the third dummy group;
• and
• the second dummy group overlapping the fourth dummy group.