Flip flop including serial stack structure transistors

A dynamic flip flop comprising:

• a dynamic circuit configured to generate a static circuit input signal according to an input signal and to a phase transition of a clock signal;
• and
• a static circuit configured to generate an output signal synchronized with the clock signal, the output signal generated according to the static circuit input signal from the dynamic circuit,
• wherein the dynamic circuit comprises,
• a precharge circuit configured to charge a first node by bridging a power voltage and the first node through which the static circuit input signal is transmitted, and
• a discharge circuit configured to discharge the first node by bridging the first node and a ground node, and
• an additional discharge circuit between the discharge circuit and the ground node includes at least two NMOS transistors arranged in parallel, the at least two NMOS transistors configured to simultaneously receive the same clock signal,
• wherein the precharge circuit comprises a plurality of PMOS transistors connected directly in series, at least two of the plurality of PMOS transistors configured to receive a same clock signal.

A flip flop comprising:

• a precharge circuit configured to charge a first node by bridging a power voltage node and the first node according to a voltage level of a clock signal, the pre-charge circuit including at least two PMOS transistors arranged in series;
• a discharge circuit configured to discharge the first node by bridging the first node and a ground node according to an input signal and the clock signal;
• a second node configured to be charged or discharged according to a voltage level of the first node;
• a first transistor and a second transistor, the first transistor and the second transistor connecting the first node to the discharge circuit,
• wherein the first transistor and the second transistor are connected to each other in parallel and respectively receive the clock signal, and
• the precharge circuit, the first transistor, and the second transistor have a layout identical to a layout of a NOR gate configured to receive two inputs.