US 12,015,402 B1Granted

Asynchronous consensus circuit with stacked ferroelectric non-planar capacitors

AssigneeKepler Computing Inc.

InventorsAmrita Mathuriya, Nabil Imam, Ikenna Odinaka, Rafael Rios, Rajeev Kumar Dokania, Sasikanth Manipatruni

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Abstract

Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Claims20

Dependent claims

An apparatus comprising:

a first input;
a second input;
and
a consensus circuitry coupled to the first input and the second input, wherein the consensus circuitry is to generate a consensus output which is indicative of a consensus of the first input and the second input, wherein the consensus circuitry comprises a gate to receive the first input, the second input, and a third input, wherein the third input is coupled to an output of the gate which is the consensus output, and wherein the gate comprises:
a first capacitor having a first terminal coupled to the first input, and a second terminal coupled to a summing node, wherein the first capacitor includes a first ferroelectric material;
a second capacitor having a third terminal coupled to the second input, and a fourth terminal coupled to the summing node, wherein the second capacitor includes a second ferroelectric material;
and
a third capacitor having a fifth terminal coupled to the third input, and a sixth terminal coupled to the summing node, wherein the third capacitor includes a third ferroelectric material, and wherein the first capacitor, the second capacitor, and the third capacitor are non-planar stacked capacitors.

5 more elements

An apparatus comprising:

a first input;
a second input;
a third input;
a fourth input;
a fifth input;
and
a gate to provide an output which is a consensus of the first input, the second input, and the third input, wherein the output is coupled to the fourth input and the fifth input, wherein the gate has a plurality of capacitors that are non-planar capacitors having ferroelectric material, and wherein the non-planar capacitors are vertically stacked.

4 more elements

A system comprising:

a memory to store one or more instructions;
a processor circuitry to execute the one or more instructions;
and
a communication device to allow the processor circuitry to communicate with another device, wherein the processor circuitry includes a consensus circuitry which comprises:
a first input;
a second input;
and
a consensus circuitry coupled to the first input and the second input, wherein the consensus circuitry is to generate a consensus output which is indicative of a consensus of the first input and the second input, wherein the consensus circuitry comprises a gate to receive the first input, the second input, and a third input, and wherein and the third input is coupled to an output of the gate which is the consensus output, and wherein the gate comprises:
a first capacitor having a first terminal coupled to the first input, and a second terminal coupled to a summing node, wherein the first capacitor includes a first ferroelectric material;
a second capacitor having a third terminal coupled to the second input, and a fourth terminal coupled to the summing node, wherein the second capacitor includes a second ferroelectric material;
and
a third capacitor having a fifth terminal coupled to the third input, and a sixth terminal coupled to the summing node, wherein the third capacitor includes a third ferroelectric material, and wherein the first capacitor, the second capacitor, and the third capacitor are non-planar stacked capacitors.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/648,124Filed 14 Jan 2022 · continuation
Priority: 13 Jan 2022
Granted: 18 Jun 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H03K 19/0021
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: modifications of threshold
G06F 13/1668
For access to memory bus: details of memory controller
G06F 30/398
Circuit design at the physical level: design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or…
G11C 11/221
Using ferroelectric elements: using ferroelectric capacitors

Family

Application17/647,963Parent of this continuation · filed 13 Jan 2022
US 11,855,627 B1Parent of this continuation
US 12,015,402 B1This patent

From the US filing history. Foreign family members aren’t listed.

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