Phased antenna array device

A phased antenna array device comprising:

• at least one input port P1 for interfacing receive and transmit RF signals to/from an antenna array;
• at least one feeding line designed to carry RF signals of two orthogonal polarizations from the at least one input port P1;
• at least one antenna feed element with an aperture or cross section having an order of symmetry C4 and supporting RF signals of two orthogonal polarizations;
• at least one first substrate from one or more substrates containing a plurality of antenna elements integrated into the at least one first substrate, with each antenna element capable of operating at two orthogonal polarizations;
• diplexer junctions integrated into the at least one first substrate, with each diplexer junction operating at two orthogonal polarizations, wherein at least one of the plurality of antenna elements are connected to the diplexer junctions;
• a plurality of phase shifters connected to corresponding antenna elements, each phase shifter operating at two orthogonal polarizations, an output port of each phase shifter being connected to a short circuit,
• wherein respective ones of the plurality of phase shifters (PS1-PS1(?)) are connected to corresponding transmission ports of the diplexer junctions;
• a plurality of orthomode transducers (OMTs) connected to corresponding output receive ports of the diplexer junctions (D1-Dn) with each OMT performing separation of orthogonally polarized signals inside a receive frequency band;
• and
• a first plurality of RF IC chips (D1-Dj) each containing an LNA, PLL frequency synthesizer and downconverter connected to corresponding receive output ports of each OMT, with each IC chip performing RF processing inside the receive frequency band, including amplification and down-conversion, for each of the two orthogonal polarizations separated by the OMT in use, the output port of each IC chip being connected to a corresponding combiner,
• wherein, in use, a first receive beam is formed using plurality of synchronization signals fed into the one or more substrates via a synchronization bus Bs and connected to the synchronization inputs of the PLL frequency synthesizers via switches (S11-S1j) so as to allow a selection of the relative phase of the LO signal generated by each PLL.