Lightly-doped channel extensions
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Jen Lai, Wei-Yuan Lu, Chih-Hao Yu, Chia-Pin Lin
Life of this patent
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Abstract
A semiconductor structure and a method of forming the same are provided. A semiconductor structure according to the present disclosure includes a first channel member and a second channel member disposed over the first channel member, a first channel extension feature coupled to the first channel member, a second channel extension feature coupled to the second channel member, and an inner spacer feature disposed between the first channel extension feature and the second channel extension feature.
Claims20
A semiconductor structure, comprising:
- a plurality of nanostructures disposed over a substrate;
- a plurality of channel extension features, each of the plurality of channel extension features being in direct contact with an end surface of one of the plurality of nanostructures;
- a source/drain feature disposed over the substrate and in direct contact with the plurality of channel extension features;
- a plurality of inner spacer features interleaving the plurality of nanostructures;
- and
- a bottom epitaxial feature sandwiched between the substrate and the source/drain feature,
- wherein the plurality of channel extension features and the bottom epitaxial feature are of a same composition,
- wherein the plurality of inner spacer features are in direct contact with the plurality of nanostructures.
A semiconductor structure, comprising:
- a substrate;
- a first source/drain feature and a second source/drain feature disposed over the substrate;
- a plurality of channel members extending between the first source/drain feature and the second source/drain feature along a direction;
- a first plurality of channel extension features disposed between the first source/drain feature and the plurality of channel members along the direction;
- and
- a first plurality of inner spacer features interleaving and in contact with the first plurality of channel extension features as well as the plurality of channel members.
A method, comprising:
- receiving a workpiece comprising:
- a substrate, and
- a fin-shaped structure over the substrate and comprising a channel region and a source/drain region adjacent the channel region, wherein the fin-shaped structure comprises a plurality of channel layers interleaved by a plurality of sacrificial layers;
- forming a dummy gate stack over the channel region;
- recessing the source/drain region to form a source/drain trench that exposes portions of the substrate, sidewalls of the plurality of channel layers and the plurality of sacrificial layers;
- selectively and partially recessing the plurality of sacrificial layers to form a plurality of inner spacer recesses;
- forming a plurality of inner spacer features in the plurality of inner spacer recesses;
- after the forming of the plurality of inner spacer features, selectively trimming the plurality of channel layers to form end surfaces;
- selectively depositing a semiconductor layer on the end surfaces and the exposed portions of the substrate to form channel extension features in contact with the end surfaces and bottom epitaxial features on the portions of the substrate;
- after the selectively depositing, forming a source/drain feature in the source/drain trench to be in contact with the channel extension features;
- and
- after the forming of the source/drain feature, replacing the dummy gate stack with a gate structure.
Dependencies are inferred from the claim text.