Thin-sheet FinFET device

A device comprising:

• a conductive fin disposed on a substrate, the conductive fin including a first sidewall and an opposing second sidewall and a top surface extending between the first and second sidewalls;
• a dielectric material layer including a first portion disposed directly on the first sidewall of the conductive fin and a second portion disposed directly on the second sidewall of the conductive fin;
• a two-dimensional material layer disposed directly on the first and second portions of the dielectric material layer, wherein a first channel region is defined in the two-dimensional material layer;
• and
• a gate stack disposed on the conductive fin, the gate stack including a gate dielectric layer and a gate electrode layer, the gate dielectric layer physically contacting the first channel region of the two-dimensional material layer.

A device comprising:

• a rib structure disposed on a substrate, the rib structure including a first sidewall and an opposing second sidewall and a top surface extending between the first and second sidewalls;
• a dielectric isolation structure disposed on the substrate adjacent the rib structure, the dielectric isolation structure having a top surface facing away from the substrate;
• a material layer disposed directly on the first and second sidewalls of the rib structure, wherein a first channel region and a first source/drain region are defined in the material layer disposed directly on the first sidewall and a second channel region and a second source/drain region are defined in the material layer disposed directly on the second sidewall, the material layer including a transition metal dichalcogenide, wherein the material layer further includes a first portion disposed directly on the top surface of the dielectric isolation structure and extending laterally away from the rib structure, wherein the first portion of the material layer has a bottom surface facing and physically contacting the top surface of the dielectric isolation structure and an opposing top surface that faces away from the top surface of the dielectric isolation structure;
• and
• a gate stack disposed on the rib structure, the gate stack including a gate dielectric layer and a gate electrode layer, the gate dielectric layer physically contacting the first and second channel regions of the material layer, wherein the gate stack further includes a first portion extending laterally away from the rib structure such that the first portion of the gate stack is disposed directly over the first portion of the material layer and the top surface of the dielectric isolation structure, the gate dielectric layer of the first portion of the gate stack having a bottom surface facing and physically contacting the top surface of the dielectric isolation structure and the top surface of the first portion of the material layer.