Gate structure and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Chun Chen, Tsung Fan Yin, Li-Te Hsu, Ying Ting Hsia, Yi-Wei Chiu
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Abstract
A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.
Claims20
A structure comprising:
- a first source/drain region and a second source/drain region in a substrate;
- and
- a gate structure over the substrate and disposed between the first source/drain region and the second source/drain region, the gate structure comprising:
- a gate dielectric;
- a cap layer on the gate dielectric;
- a gate electrode;
- and
- a work function tuning structure between the gate dielectric and the gate electrode, the work function tuning structure having sidewalls separated by a first dimension distal the substrate and by a second dimension less than the first dimension proximal the substrate, wherein the work function tuning structure comprises:
- a first work function tuning layer in contact with the cap layer;
- a second work function tuning layer in contact with the first work function tuning layer and the cap layer;
- and
- a third work function tuning layer in contact with the second work function tuning layer and the cap layer.
A semiconductor device comprising:
- a semiconductor substrate;
- a first source/drain region and a second source/drain region in the semiconductor substrate;
- and
- a gate structure on the semiconductor substrate between the first source/drain region and the second source/drain region, the gate structure comprising:
- a gate dielectric layer;
- a cap layer lining the gate dielectric layer;
- a first work function metal layer lining and contacting the cap layer;
- and
- a second work function metal layer lining and contacting the first work function metal layer and the cap layer;
- a third work function metal layer lining and contacting the second work function metal layer and the cap layer;
- and
- a gate electrode lining and contacting the third work function metal layer.
A semiconductor device comprising:
- a first source/drain region and a second source/drain region in a substrate;
- and
- a gate structure over the substrate and disposed between the first source/drain region and the second source/drain region, the gate structure comprising:
- a gate dielectric;
- a cap layer lining the gate dielectric;
- a gate electrode;
- a work function tuning structure disposed between the gate dielectric and the gate electrode, the work function tuning structure comprising:
- a first work function layer lining and contacting the cap layer;
- and
- a second work function layer lining and contacting the first work function layer and the cap layer;
- a gate spacer on a sidewall of the gate structure;
- and
- a dielectric cap on the gate structure, wherein a first uppermost surface of the gate spacer is level with a second uppermost surface of the dielectric cap, and wherein the first uppermost surface and the second uppermost surface are above a third uppermost surface of the gate structure.
Dependencies are inferred from the claim text.