Triple layer high-k gate dielectric stack for workfunction engineering

A semiconductor structure, comprising:

• a substrate;
• a first stack of channel layers over the substrate in an NFET region;
• a second stack of channel layers over the substrate in a PFET region;
• an interfacial layer surrounding each layer of the first and the second stacks of channel layers;
• a first gate dielectric layer over the interfacial layer, wherein a first portion of the first gate dielectric layer surrounds each of the first stack of channel layers and includes hafnium oxide, and a second portion of the first gate dielectric layer surrounds each of the second stack of channel layers and includes a compound of hafnium oxide and a first metal, wherein the first metal includes niobium, wherein the first and the second portions of the first gate dielectric layer include different materials;
• a second gate dielectric layer over the first gate dielectric layer, wherein a first portion of the second gate dielectric layer surrounds each of the first stack of channel layers and includes a compound of hafnium oxide and a second metal, wherein the second metal includes yttrium, and a second portion of the second gate dielectric layer surrounds each of the second stack of channel layers and includes hafnium oxide, wherein the first and the second portions of the second gate dielectric layer include different materials;
• a third gate dielectric layer over the second gate dielectric layer and surrounding each layer of the first and the second stacks of channel layers, wherein the third gate dielectric layer comprises hafnium oxide;
• and
• a gate work function metal layer over the third gate dielectric layer and surrounding each layer of the first and the second stacks of channel layers, wherein a portion of each of the first, the second, and the third gate dielectric layers is disposed on the substrate and below another portion of the third gate dielectric layer under a bottommost layer of the first and the second stacks of channel layers.

A semiconductor structure, comprising:

• a substrate;
• a first stack of channel layers over the substrate in an NFET region;
• a second stack of channel layers over the substrate in a PFET region;
• a first gate stack at least laterally surrounding each of the first stack of channel layers;
• and
• a second gate stack at least laterally surrounding each of the second stack of channel layers,
• wherein the first gate stack includes a first portion of a first gate dielectric layer, a first portion of a second gate dielectric layer over the first portion of the first gate dielectric layer, a first portion of a third gate dielectric layer over the first portion of the second gate dielectric layer, and a first portion of a gate work function metal layer over the first portion of the third gate dielectric layer,
• wherein the second gate stack includes a second portion of the first gate dielectric layer, a second portion of the second gate dielectric layer over the second portion of the first gate dielectric layer, a second portion of the third gate dielectric layer over the second portion of the second gate dielectric layer, and a second portion of the gate work function metal layer over the second portion of the third gate dielectric layer,
• wherein the first and the second portions of the first gate dielectric layer include different materials, the first and the second portions of the first gate dielectric layer both include a first high-k dielectric material, the second portion of the first gate dielectric layer further includes a first metal such that a compound of the first high-k dielectric material and the first metal provides an upward adjustment to a work function of the second gate stack, the first metal includes Nb, Ga, Zn, or Ti,
• wherein the first and the second portions of the second gate dielectric layer include different materials, the first and the second portions of the second gate dielectric layer both include a second high-k dielectric material, the first portion of the second gate dielectric layer further includes a second metal such that a compound of the second high-k dielectric material and the second metal provides a downward adjustment to a work function of the first gate stack.