Ring structure for film resistor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChun-Tsung Kuo, Jiech-Fun Lu
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Abstract
Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes depositing a resistive layer over a substrate. A conductive structure is formed over the resistive layer. A first etch process is performed on the resistive layer to define a resistor segment of the resistive layer and a peripheral region of the resistive layer. The resistor segment is laterally separated from the peripheral region of the resistive layer. The peripheral region continuously laterally wraps around an outer perimeter of the resistor segment.
Claims20
A method for forming an integrated chip, comprising:
- depositing a resistive layer over a substrate;
- forming a conductive structure over the resistive layer;
- and
- performing a first etch process on the resistive layer to define a resistor segment of the resistive layer and a peripheral region of the resistive layer, wherein the resistor segment is laterally separated from the peripheral region of the resistive layer, and wherein the peripheral region continuously laterally wraps around an outer perimeter of the resistor segment.
A method for forming a semiconductor structure, comprising:
- depositing a lower dielectric layer over a substrate;
- depositing a resistor layer over the lower dielectric layer;
- and
- forming an isolation structure over the lower dielectric layer, wherein the isolation structure extends through the resistor layer and envelopes a perimeter of a resistor segment of the resistor layer, wherein forming the isolation structure comprises:
- patterning the resistor layer to define an opening that surrounds the resistor segment;
- depositing a dielectric liner over the resistor layer, wherein the dielectric liner lines the opening;
- and
- forming a conductive body within the opening, wherein the dielectric liner separates the conductive body from the resistor layer.
A method of forming an integrated chip, comprising:
- depositing a resistive layer over a substrate, wherein the resistive layer comprises a first material;
- forming a conductive structure over the resistive layer, wherein the conductive structure comprises a second material different than the first material;
- forming an inter-level dielectric (ILD) structure over the conductive structure;
- patterning the ILD structure and the resistive layer to define a plurality of via openings and a ring structure opening, such that the ring structure opening laterally encloses a resistor segment of the resistive layer, wherein the ring structure opening extends from an upper surface of the ILD structure to a point below the resistive layer;
- forming a plurality of conductive vias in the plurality of via openings;
- and
- forming a ring structure within the ring structure opening.
Dependencies are inferred from the claim text.