High density interconnection and wiring layers, package structures, and integration methods

A method of forming a semiconductor device, the method comprising:

• forming a coreless laminate substrate;
• forming a first plurality of electrical devices in or on a surface of the laminate substrate;
• forming interconnection ports at the first plurality of electrical devices;
• forming a redistribution layer on a handle layer, the redistribution layer having a second plurality of electrical devices on or in a surface of the redistribution layer;
• connecting the redistribution layer to the laminate substrate using the handle layer such that the second plurality of electrical devices is interconnected to the first plurality of electrical devices through the interconnection ports;
• wherein when the redistribution layer is connected to the laminate substrate, the surface of the laminate substrate and the surface of the redistribution layer are parallel to each other.

A method for fabricating an interconnect for a semiconductor device, the method comprising:

• forming a multi-layer base substrate;
• forming a first plurality of electrical and/or optical semiconductor devices in or on a surface of the multi-layer base substrate;
• forming first ends of interconnection ports at the first plurality of electrical and/or optical semiconductor devices;
• forming a second plurality of electrical and/or optical semiconductor devices at second ends of the interconnection ports distal from the first ends;
• forming a redistribution layer on a handle layer, the redistribution layer having a third plurality of electrical and/or optical semiconductor devices in or on the redistribution layer;
• connecting the redistribution layer to the handle layer;
• disposing the handle layer onto the second plurality of electrical and/or optical semiconductor devices;
• and
• removing the handle layer;
• wherein the surface of the multi-layer base substrate and the surface of the redistribution layer are parallel to each other to form dielectric and conductor structures.