Semiconductor device

A method of manufacturing a semiconductor device comprising:

• forming a transistor on a substrate;
• forming a first interlayer insulating layer on the transistor;
• forming a lower interconnection line in an upper portion of the first interlayer insulating layer;
• forming an etch stop layer on the first interlayer insulating layer and the lower interconnection line;
• forming a first surface treatment region and a second surface treatment region that are adjacent to opposing sides of the lower interconnection line, respectively, and formed in the etch stop layer;
• selectively forming a first etch stop pattern and a second etch stop pattern on the first and second surface treatment regions, respectively, the first and second etch stop patterns defining a groove;
• forming a second interlayer insulating layer on the first and second etch stop patterns and the etch stop layer;
• forming an interconnection line hole in an upper portion of the second interlayer insulating layer;
• forming a via hole penetrating the etch stop layer along the groove and exposing a top surface of the lower interconnection line;
• and
• forming an upper interconnection line in the interconnection line hole and the via hole.

A method of manufacturing a semiconductor device comprising:

• forming a transistor on a substrate;
• forming a first interlayer insulating layer on the transistor;
• forming a lower interconnection line in an upper portion of the first interlayer insulating layer;
• forming an etch stop layer on the first interlayer insulating layer and the lower interconnection line;
• forming an etch stop pattern on a surface treatment region of the etch stop layer;
• forming a second interlayer insulating layer on the etch stop pattern and the etch stop layer;
• forming an interconnection line hole in an upper portion of the second interlayer insulating layer;
• forming a via hole penetrating the etch stop pattern and the etch stop layer and exposing a top surface of the lower interconnection line;
• and
• forming an upper interconnection line in the interconnection line hole and the via hole,
• wherein the via hole exposing the etch stop pattern has a first width in a first direction
• wherein a maximum width of the etch stop pattern in the first direction is a second width, and
• wherein the second width ranges from about 1.2 times to about 3 times the first width.