Chip package structure including a silicon substrate interposer and methods for forming the same

A method of forming a chip package structure, the method comprising:

• forming a package-side redistribution structure over a carrier substrate;
• forming an interposer core assembly on a top surface of the package-side redistribution structure, wherein the interposer core assembly comprises at least one silicon substrate interposer and a molding compound interposer frame that surrounds the at least one silicon substrate interposer, wherein one of the at least one silicon substrate interposer comprises metal bonding structures which are topmost components of vertical signal paths that vertically extends through said one of the at least one silicon substrate interposer;
• forming a die-side redistribution structure comprising die-side redistribution wiring interconnects over the interposer core assembly, where the die-side redistribution wiring interconnects comprise via structures that are formed directly on surfaces of the metal bonding structures;
• and
• attaching at least two semiconductor dies to the die-side redistribution structure.

A method of forming a chip package structure, the method comprising:

• forming a package-side redistribution structure over a carrier substrate;
• forming an interposer core assembly on a top surface of the package-side redistribution structure, wherein the interposer core assembly comprises at least one silicon substrate interposer, a molding compound interposer frame that surrounds the at least one silicon substrate interposer, and through-molding-compound via (TMCV) structures that vertically extend through the molding compound interposer frame;
• forming a die-side redistribution structure over the interposer core assembly, wherein the TMCV structures electrically connect a respective pair of a die-side redistribution wiring interconnect within the die-side redistribution structure and a package-side redistribution wiring interconnect within the package-side redistribution structure;
• and
• attaching at least two semiconductor dies to the die-side redistribution structure, wherein:
• one of the at least two semiconductor dies comprises a system-on-chip (SoC) die;
• another of the at least two semiconductor dies comprises a high bandwidth memory (HBM) die;
• and
• at least one set of metal interconnect structures within the at least one silicon substrate interposer is configured to provide electrically conductive paths that connect the SoC die and the HBM die, and are electrically isolated from package-side redistribution wiring interconnects within the package-side redistribution structure.