Method of semiconductor overlay measuring and method of semiconductor structure manufacturing

A method of semiconductor overlay measuring, comprising:

• providing a test substrate, wherein a plurality of conductive structures are disposed in the test substrate and exposed from a top surface of the test substrate;
• positioning the test substrate to a standard position and capturing a first image of the top surface of the test substrate;
• marking a plurality of first marks on the first image, wherein the first marks are direct to the exposed conductive structures within the test substrate in the first image;
• after the first image is captured, forming a test capping layer on the top surface of the test substrate, wherein the test capping layer has a plurality of capacitor openings;
• moving the test substrate to the standard position and capturing a second image of a top surface of the test capping layer;
• identifying the capacitor openings on the second image with a plurality of second marks;
• and
• comparing the first marks with the second marks to determine a position offset between the test substrate and the test capping layer.