Word line driver array and memory

A word line driver array, comprising:

• a first transistor, a third transistor, a fourth transistor and a second transistor arranged sequentially, as well as a fourth word line, a first word line, a second word line and a third word line parallel to each other, wherein the fourth word line is connected to a drain of the fourth transistor, the first word line is connected to a drain of the first transistor, the second word line is connected to a drain of the second transistor, and the third word line is connected to a drain of the third transistor;
• and
• wherein a direction that a source of a transistor faces toward a drain of the transistor is recorded as a source-drain orientation of the transistor, and source-drain orientations of adjacent transistors are opposite;
• and
• wherein gates of the adjacent transistors are at least partially staggered in an arrangement direction of word lines;
• and
• wherein in the arrangement direction of the word lines, a gate of the third transistor is located between a gate of the fourth transistor and a gate of the second transistor;
• and
• wherein in the arrangement direction of the word lines, a source of the third transistor is located between the drain of the fourth transistor and a source of the second transistor, and the drain of the third transistor is located between a source of the fourth transistor and the drain of the second transistor.