Semiconductor storage device having bit line selection circuit formed in memory cell array
AssigneeWinbond Electronics Corp.
InventorNaohito Morozumi
Life of this patent
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Abstract
The disclosure provides a semiconductor storage device that realizes high integration and improves reliability. A bit line selection circuit (100) of a flash memory includes transistors (BLSeO, BLSeE, BLSoO, BLSoE) in the column direction of bit lines (BL0-BL3), selecting a bit line pair composed of an even-numbered bit line (BL0) and an odd-numbered bit line (BL3) is selected by the transistors, in which a bit line pair (BL1, BL2) adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair (BL0, BL3) is connected to page buffer/sensing circuit through an output node (BLS0, BLS1).
Claims14
A semiconductor storage device, comprising:
- a memory cell array, comprising a plurality of NAND strings and a bit line selection circuit, the plurality of NAND strings respectively connected to a plurality of bit lines;
- and
- a page buffer/sensing circuit connected to the bit line selection circuit,
- wherein the bit line selection circuit is configured to select a bit line pair composed of an even-numbered bit line and an odd-numbered bit line, in which a bit line pair adjacent to the selected bit line pair is set as a non-selected bit line pair, and the selected bit line pair is connected to the page buffer/sensing circuit via an output node of the bit line selection circuit.
Dependencies are inferred from the claim text.