Memory device and method of operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsMeng-Sheng Chang, Ku-Feng Lin
Life of this patent
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Abstract
A memory device includes a plurality of memory cells including a first memory cell and a second memory cell, a first bit line connected to the first memory cell, a second bit line connected to the second memory cell, a first word line connected to the first and second memory cells, a first control transistor connected to the first bit line, a second control transistor connected to second bit line, a first mux transistor commonly connected to the first and second control transistors, and a sense amplifier connected to the first mux transistor.
Claims20
A memory device, comprising:
- a plurality of memory cells including a first memory cell and a second memory cell, wherein the first and second memory cells share a first word line transistor;
- a first bit line connected to the first memory cell;
- a second bit line connected to the second memory cell;
- a first word line connected to the first word line transistor shared by the first and second memory cells;
- a first control transistor connected to the first bit line;
- a second control transistor connected to second bit line;
- a first mux transistor commonly connected to the first and second control transistors;
- and
- a sense amplifier connected to the first mux transistor.
A method of operating a memory device, comprising:
- activating, during a read operation of a first memory cell, a first word line connected to a first word line transistor shared by the first memory cell and a second memory cell;
- activating a first control gate line connected to the first memory cell;
- activating a mux control line connected to a mux transistor, the mux transistor connected to a sense amplifier;
- and
- activating a common gate signal line connected to a gate terminal of a first common gate transistor connected to the first memory cell and a gate terminal of a second common gate transistor connected to the second memory cell.
A memory system, comprising:
- a plurality of memory cells including a first memory cell and a second memory cell, wherein the first and second memory cells share a first word line transistor;
- a sense amplifier connected to the plurality of memory cells via a plurality of bit lines;
- and
- a controller connected to the plurality of memory cells, wherein the controller is configured to:
- activate, during a read operation of a first memory cell, a first word line connected to the first word line transistor shared by the first memory cell and a second memory cell;
- activate a first control gate line connected to the first memory cell;
- activate a mux control line connected to a mux transistor, the mux transistor connected to a sense amplifier;
- and
- activate a common gate signal line connected to a gate terminal of a first common gate transistor connected to the first memory cell and a gate terminal of a second common gate transistor connected to the second memory cell.
Dependencies are inferred from the claim text.