Double sense amp and fractional bit assignment in non-volatile memory structures

A memory controller, comprising:

• a first communication pathway configured to couple to a non-volatile memory structure;
• and
• the memory controller configured to:
• initiate a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, the memory structure comprising:
• a first memory array corresponding to a floor of the memory structure, the first memory array comprising a first population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the first memory array is disposed below the first population of the plurality of memory cells;
• a second memory array corresponding to a ceiling of the memory structure and:
• electrically coupled to and interconnected with the first memory array via a continuous communication pathway such that the first memory array and the second memory array operate as a contiguous memory device;
• vertically inverted relative to and positioned on top of the first memory array;
• and
• comprising a second population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the second memory array is disposed above the second population of the plurality of memory cells;
• and
• a data bus tap electrically coupling the first memory array and to the second memory array.

A non-volatile memory system, comprising:

• a memory structure, comprising:
• a first memory array corresponding to a floor of the memory structure, the first memory array comprising a first population of a plurality of memory cells of the memory structure and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the first memory array is disposed below the first population of the plurality of memory cells;
• a second memory array corresponding to a ceiling of the memory structure and:
• electrically coupled to and interconnected with the first memory array via a continuous communication pathway such that the first memory array and the second memory array operate as a contiguous memory device;
• vertically inverted relative to and positioned on top of the first memory array;
• and
• comprising a second population of the plurality of memory cells and associated peripheral circuitry, wherein the associated peripheral circuitry including all sense amplifiers for the second memory array is disposed above the second population of the plurality of memory cells;
• and
• a data bus tap electrically coupling the first memory array and the second memory array;
• and
• a memory controller coupled to the memory structure and initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of the plurality of memory cells of the memory structure.