US 12,014,789 B2 · Apparatuses, systems, and methods for error correction

Abstract

Apparatuses, systems, and methods for error correction. A memory device may have a number of memory cells each of which stores a bit of information. A first latch may hold the encoded bit and provide it as a write parity bit to the memory array as part of a write operation. A second latch may hold a parity bit read from the memory array and the ECC circuit may generate a command signal based on that parity bit. A multiplexer latch may hold the encoded bit and provide a syndrome bit based on the command signal and the encoded bit. The syndrome bit may indicate if there is mismatch between the parity bit and the encoded bit. The logic which handles generating the syndrome bit may be separated from the logic tree.

Claims22

Dependent claims

A method comprising:

receiving a first plurality of bits from an input/output circuit as part of a write operation to a memory array;
generating a first encoded bit based on the first plurality of bits with a logic tree;
storing the first encoded bit in a first latch;
writing the first encoded bit from the first latch and the first plurality of bits from the input/output circuit in parallel to the memory array;
reading a second plurality of bits and a parity bit from the memory array as part of a read operation;
storing the parity bit in a second latch;
generating a second encoded bit based on the second plurality of bits with the logic tree;
and
comparing the parity bit stored in the second latch to the second encoded bit from the logic tree.

6 more elements

An apparatus comprising:

a memory array configured to store a plurality of data bits and at least one associated parity bit;
and
an error correction code (ECC) circuit comprising:
a logic tree configured to receive a plurality of input bits and generate at least one encoded bit as part of a read operation or a write operation;
a read path configured to receive the plurality of data bits as a plurality of read data bits and the at least one associated parity bit as at least one read parity bit from the memory array as part of the read operation, provide the plurality of read data bits to the logic tree as the plurality of input bits, and compare the at least one encoded bit generated based on the plurality of read data bits to the at least one associated read parity bit read from the memory array to generate at least one syndrome bit;
and
a write path configured to receive a plurality of write data bits from an input/output circuit as part of the write operation, provide the plurality of write data bits to the logic tree as the plurality of input bits to generate the at least one encoded bit as at least one write parity bit, and write the plurality of write data bits to the memory array as the plurality of data bits and write the at least one write parity bit as the at least one associated parity bit.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

17/813,079Filed 18 Jul 2022 · continuation

Priority

7 Feb 2020

Published

US 2022/0351800 A13 Nov 2022

Granted

18 Jun 2024

Term ends

Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 11/4093
Read-write [R-W] circuits: input/output [I/O] data interface arrangements, e.g. data buffers
G11C 29/42
Response verification devices: using error correcting codes [ECC] or parity check
G06F 11/1048
In individual solid state devices: using arrangements adapted for a specific error detection or correction feature
G11C 7/106
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output latches

Apparatuses, systems, and methods for error correction

Life of this patent

Apparatuses, systems, and methods for error correction

Life of this patent

Abstract

Claims22