Memory array detection circuit and detection method, and memory

A memory array detection method, comprising:

• writing, by a write circuit, same initial data into each memory cell of the memory array;
• reading, by a read circuit, data stored in each memory cell of the memory array;
• comparing, by a data compression circuit, data read from memory cells of the memory array, and detecting whether the memory array is defective according to whether the read data are identical;
• wherein the memory array comprises multiple memory matrixes, each of the multiple memory matrixes comprises multiple memory sub-arrays, and each of the multiple memory sub-arrays comprises multiple memory cells;
• all memory sub-arrays in the memory array are divided into at least four memory sub-array groups, data in memory cells corresponding to each of the at least four memory sub-array groups are output through a same transmission sub-interface, and a number of transmission sub-interfaces is identical to a number of the at least four memory sub-array groups;
• wherein the data compression circuit comprises a first data compression circuit and a second data compression circuit, and the method further comprises:
• comparing, by the first data compression circuit for each of the transmission sub-interfaces, data output by the transmission sub-interface to determine whether data in multiple memory cells output by the transmission sub-interface are identical;
• in response to that the data in the multiple memory cells output by the transmission sub-interface are not identical, determining that the memory array is defective;
• in response to that the data in the multiple memory cells output by each of the transmission sub-interfaces are identical, performing further comparison by the second data compression circuit by:
• for each two of the transmission sub-interfaces, comparing data output by the two of the transmission sub-interfaces to determine whether the data output by the two of the transmission sub-interfaces are identical;
• in response to that the data output by the two of the transmission sub-interfaces are not identical, determining that the memory array is defective;
• and
• in response to that the data output by each two of the transmission sub-interfaces are identical and the output data are identical to the initial data, determining that the memory array is not defective.

A memory array detection method, comprising:

• writing, by a write circuit, same initial data into each memory cell of the memory array;
• reading, by a read circuit, data stored in each memory cell of the memory array;
• comparing, by a data compression circuit, data read from memory cells of the memory array, and detecting whether the memory array is defective according to whether the read data are identical;
• wherein the memory array comprises multiple memory matrixes that are divided into at least four memory matrix groups, each of the at least four memory matrix groups outputs data through a respective first transmission sub-interface, a number of first transmission sub-interfaces is identical to a number of the at least four memory matrix groups;
• and
• each of the multiple memory matrixes comprises multiple memory sub-arrays, and each of the multiple memory sub-arrays comprises multiple memory cells;
• the multiple memory sub-arrays in each of the multiple memory matrixes are divided into at least four memory sub-array groups that output data through second transmission sub-interfaces respectively, and the second transmission sub-interfaces are in one-to-one correspondence to the at least four memory sub-array groups;
• wherein the data compression circuit comprises a first data compression circuit and a second data compression circuit, and the method further comprises:
• operation a) acquiring, for a first memory matrix group through a corresponding first transmission sub-interface by the first data compression circuit, data output by all corresponding second transmission sub-interfaces, and determining, for each of the corresponding second transmission sub-interfaces, whether data of multiple memory cells output by the second transmission sub-interface are identical;
• operation b) in response to that the data of the multiple memory cells output by the second transmission sub-interface are not identical, determining that the first memory matrix group is defective;
• operation c) in response to that the data of the multiple memory cells output by each of the corresponding second transmission sub-interfaces are identical, performing further comparison by the second data compression circuit by:
• comparing data output by each two of the corresponding second transmission sub-interfaces to determine whether the data output by the two of the corresponding second transmission sub-interfaces are identical;
• operation d) in response to that the data output by the two of the corresponding second transmission sub-interfaces are not identical, determining that the first memory matrix is defective;
• operation e) in response to that the data output by each two of the corresponding second transmission sub-interfaces are identical and the output data are identical to the initial data, determining that the first memory matrix is not defective;
• performing same operations a) to e) for remaining memory matrixes in the memory array other than the first memory matrix;
• operation f) in response to that data in memory cells of all memory matrixes of the memory array are identical and the output data are identical to the initial data, determining that the memory array is not defective.