Memory device supporting interleaved operations and memory system including the same

A memory system, comprising:

• a first memory die including multiple first planes each including a plurality of first memory cells;
• a second memory die including multiple second planes each including a plurality of second memory cells;
• and
• a controller configured to perform data communication with the first and second memory dies through first and second channels,
• wherein the controller is configured to transfer at least two commands from among commands for an erase operation, a read operation, a program operation, and a check operation to be performed in the first and second memory dies, and
• wherein the first memory die is configured to, while performing an erase operation in a plane of the multiple first planes based on commands input from the controller, perform a read operation, a program operation or a check operation in other planes of the multiple first planes based on the commands, and
• wherein the controller is configured to estimate an operation margin of the erase operation performed in the plane and adjust or change a sequence of the read command, the program command, and the check command to be transferred to the other planes.

A memory device, comprising:

• a plurality of non-volatile memory cells divided into multiple groups;
• a control circuit configured to change or adjust an execution sequence of an erase operation, a program operation, a read operation, and a check operation performed on the plurality of non-volatile memory cells, and, while performing an erase operation in a group of the multiple groups, perform a read operation, a program operation, or a check operation in other groups of the multiple groups, and
• multiple data buffers and multiple command buffers, each data buffer and each command buffer corresponding to a group of the multiple groups,
• wherein the control circuit is configured to control input or output of the multiple data buffers and the multiple command buffers to change or adjust the execution sequence, and
• wherein the control circuit is configured to, when a command output from a command buffer among the multiple command buffers is an erase command, check whether an operation performed in the multiple groups is an erase operation to determine whether an operation corresponding to the command is executed.