Memory circuit, memory device and operation method thereof
AssigneeNational Central University
InventorE Ray Hsieh
Life of this patent
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Abstract
The present disclosure provides a memory device, which includes a plurality of electrically bipolar variable memory devices and a storage transistor. The electrically bipolar variable memory devices are electrically connected to a plurality of word lines respectively, the storage transistor is electrically connected to the electrically bipolar variable memory devices, where one end of each of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the word lines, and another end of each of the electrically bipolar variable memory devices is electrically connected to the gate of the storage transistor.
Claims19
A memory device, comprising:
- a plurality of electrically bipolar variable memory devices electrically connected to a plurality of word lines respectively;
- and
- a storage transistor electrically connected to the plurality of the electrically bipolar variable memory devices, wherein one end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the plurality of the word lines, and another end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a gate of the storage transistor,
- wherein the storage transistor comprises:
- the gate comprising one electrically conductive layer or a plurality of electrically conductive layers disposed above one dielectric layer or a plurality of dielectric layers disposed above a semiconductor substrate, the gate contacting one end of a gate contact plug, another end of the gate contact plug contacting a metal layer, and the plurality of the electrically bipolar variable memory devices formed on the metal layer;
- and a source/drain and another source/drain formed in the semiconductor substrate, and a channel region positioned between said source/drains under the gate rendering electrical signals.
A memory circuit, comprising:
- a plurality of memory devices arranged in an array, each of the memory devices comprising:
- a plurality of electrically bipolar variable memory devices electrically connected to a plurality of word lines respectively;
- and
- a storage transistor electrically connected to the plurality of the electrically bipolar variable memory devices, wherein one end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the word lines, and another end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a gate of the storage transistor,
- wherein the storage transistor comprises:
- the gate comprising one electrically conductive layer or a plurality of electrically conductive layers disposed above one dielectric layer or a plurality of dielectric layers disposed above a semiconductor substrate, the gate contacting one end of a gate contact plug, another end of the gate contact plug contacting a metal layer, and the plurality of the electrically bipolar variable memory devices formed on the metal layer;
- and a source/drain and another source/drain formed in the semiconductor substrate, and a channel region positioned between said source/drains under the gate rendering electrical signals.
An operation method of a memory device, the memory device comprising a storage transistor and a plurality of electrically bipolar variable memory devices, the plurality of electrically bipolar variable memory devices electrically connected to a plurality of word lines respectively, and the operation method comprising steps of:
- when programming one of the plurality of electrically bipolar variable memory devices, applying a programming voltage to a corresponding word line of the plurality of word lines, applying a zero voltage to a bit line, and floating a source line, wherein one end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a corresponding one of the plurality of the word lines, another end of each of the plurality of the electrically bipolar variable memory devices is electrically connected to a gate of the storage transistor, a source/drain of the storage transistor is electrically connected to the source line, and another source/drain of the storage transistor is electrically connected to the bit line.
Dependencies are inferred from the claim text.