In-line programming adjustment of a memory cell in a memory sub-system

A method comprising:

• initiating a programming algorithm to program a memory cell to a first target voltage level representing a first programming level of a plurality of programming levels;
• causing a first programming pulse of the programming algorithm to be applied to a wordline associated with the memory cell;
• performing a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds the first target voltage level;
• causing first data to be stored in a first cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level;
• causing the first cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level;
• and
• causing, in view of the second data, a further programming pulse to be applied to the wordline associated with the memory cell at a reduced programming stress.

A memory device comprising:

• a memory array comprising a plurality of memory cells comprising a first memory cell;
• and
• control logic, operatively coupled with the memory array, to perform operations comprising:
• initiating a programming algorithm to program a memory cell to a first programming level of a plurality of programming levels;
• causing, at a first time, a first programming pulse of the programming algorithm to be applied to a wordline associated with the memory cell;
• performing a program verify operation corresponding to the first programming level to determine that a threshold voltage of the memory cell exceeds a first target voltage level;
• causing first data to be stored in a first cache, the first data indicating that the threshold voltage of the memory cell exceeds the first target voltage level;
• causing the first cache to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the first target voltage level;
• and
• causing, at a second time, in view of the second data, a further programming pulse to be applied to the wordline associated with the memory cell at a reduced programming stress level.