Memory selector threshold voltage recovery

A method comprising:

• performing a subthreshold stress process on a memory array, wherein each memory cell of the memory array comprises a chalcogenide selector, wherein performing the subthreshold stress process comprises:
• applying a first voltage between a first word line and a first bit line of the memory array, wherein a first memory cell of the memory array is connected to the first word line and the first bit line, wherein at the start of the subthreshold stress process the chalcogenide selector of the first memory cell has a first threshold voltage, wherein a magnitude of the first voltage is less than the first threshold voltage, wherein at the end of the subthreshold stress process the chalcogenide selector of the first memory cell has a second threshold voltage that is smaller than the first threshold voltage;
• and
• before performing the subthreshold stress process, applying a second voltage between the first word line and the first bit line of the memory array, wherein the second voltage is greater than the first threshold voltage, wherein a polarity of the second voltage is opposite that of the first voltage, wherein no voltage is applied between the first word line and the first bit line in the time between the applying of the second voltage and the applying of the first voltage.

A method comprising:

• determining a target threshold voltage for a chalcogenide selector, wherein the chalcogenide selector has a threshold voltage that is different than the target threshold voltage;
• applying a first voltage pulse to the chalcogenide selector, wherein a magnitude of the first voltage pulse is less than the target threshold voltage;
• after applying the first voltage pulse, applying a test voltage pulse to the chalcogenide selector, wherein the magnitude of the test voltage pulse is at least the magnitude of the target threshold voltage;
• determining whether the test voltage pulse successfully switched the chalcogenide selector into an on-state;
• and
• based on the determining of the switching of the chalcogenide selector into an on-state, applying a second voltage pulse to the chalcogenide selector, wherein a duration of the second voltage pulse is longer than a duration of the first voltage pulse and/or a magnitude of the second voltage pulse is larger than a magnitude of the first voltage pulse.