Storage controller and storage device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsDong Eun Shin, Jeong Uk Kang, Hyun Jin Choi
Life of this patent
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Abstract
A storage controller for writing first data to a first memory cell by performing programming of the first memory cell N-times, where N is a positive integer greater than 1, includes a write amplification manager and a central processing unit. The write amplification manager checks whether the first data is invalid data before an Nth programming of the first memory cell is performed, and the central processing unit does not perform the N-th programming of the first memory cell when the first data is the invalid data.
Claims20
A storage controller for writing first data to a first memory cell by performing programming of the first memory cell N-times (N being a positive integer greater than 1), the storage controller comprising:
- a write amplification (WAF) manager configured to check whether the first data is invalid data before an Nth programming of the first memory cell is performed;
- and
- a central processing unit (CPU) configured not to perform the N-th programming of the first memory cell when the first data is the invalid data.
A storage device for writing first data to a first memory cell by performing programming of the first memory cell N-times (N being a positive integer greater than 1), the storage device comprising:
- a non-volatile memory (NVM) device comprising the first memory cell;
- and
- a storage controller configured to write the first data to the first memory cell,
- wherein the storage controller comprises:
- a write amplification (WAF) manager configured to check whether the first data is invalid data before an Nth programming of the first memory cell is performed;
- and
- a central processing unit (CPU) configured not to perform the N-th programming of the first memory cell when the first data is the invalid data.
A storage device for writing first data to a first memory block and writing second data to a second memory block by performing programming of each of the first memory block and the second memory block N-times (N being a positive integer greater than 1), the storage device comprising:
- a non-volatile memory (NVM) device comprising the first memory block and the second memory block;
- and
- a storage controller configured to write the first data to the first memory block and write the second data to the second memory block,
- wherein the storage controller comprises:
- a write amplification (WAF) manager comprising an open memory cell detector configured to check whether an open memory cell exists in the first memory block or the second memory block before an Nth programming of the first memory block and the second memory block is performed, and a memory cell compactor configured to conduct memory cell compaction by moving a location of an (N−1)th-programming of a memory cell in one memory block of the first memory block and the second memory block to a memory cell in the other memory block of the first memory block and the second memory block when the open memory cell exists in the first memory block or the second memory block;
- and
- a central processing unit (CPU) configured to not perform the Nth programming of the first memory block and the second memory block after the memory cell compactor conducts the memory cell compaction.
Dependencies are inferred from the claim text.